The 5 nm node was once assumed by some experts to be the end of Moore's law. Transistors smaller than 7 nm will experience quantum tunnelling through the gate oxide layer. Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the two years estimated by Moore's law. In 2009, Intel's roadmap projected an end-user release by approximately 2020, though Intel has not yet revealed any specific plans to manufacturers or retailers.
Technology demos
Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometresilicon-on-insulator MOSFET. In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET. In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers. In 2015, Intel described a lateral nanowire FET concept for the 5 nm node. In 2017, IBM revealed that they had created 5 nm silicon chips, using silicon nanosheets in a gate-all-around configuration, a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2.
Commercialization
In early 2018, TSMC expected to begin production of a 5 nm node by 2020 on its new Fab 18. In October 2018, TSMC announced plans to start testing or "risk production" of 5 nm devices by April 2019. In April 2019, SamsungElectronics announced they had been offering their 5 nm process tools to their customers since 2018 Q4. In April 2019, TSMC announced that their 5 nm process had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++. In October 2019, TSMC started sampling 5nm A14 processors for Apple. In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm2. The yield goes down to 32.0% with an increase in die size to 100 mm2.
5 nm process nodes
Transistor gate pitch is also referred to as CPP and interconnect pitch is also referred to as MMP.
Beyond 5 nm
3 nm is the usual term for the next node after 5 nm. Samsung and TSMC have plans to commercialize the 3 nm node. 3.5 nm has also been given as a name for the first node beyond 5 nm.
