Released as the expansion bus of the CommodoreAmiga 3000 in 1990, the Zorro IIIcomputer bus was used to attach peripheral devices to an Amiga motherboard. Designed by Commodore International lead engineer Dave Haynie, the 32-bit Zorro III replaced the 16-bitZorro II bus used in the Amiga 2000. As with the Zorro II bus, Zorro III allowed for true Plug and Play autodetection wherein devices were dynamically allocated the resources they needed on boot. Zorro III continued Zorro II's direct memory-mapped address design. Just as with Zorro II on 24-bit systems, Zorro III reserved a large chunk of 32-bit real memory address space for large memory mapped cards, a smaller chunk with smaller allocation granularity for "I/O" type board. Zorro III was never supported on 24-bit address or 16-bit data devices—it required a full 32-bit CPU. The CPU could directly address any Zorro III device as memory, so Zorro memory expansions could be made as well as it being possible to use video memory on a video card to be as system RAM. As an asynchronous bus, Zorro III specified bus cycles of set lengths during which a transaction conforming to the specifications of the bus could be carried out. The initial implementation of Zorro III was in Commodore's "Fat" Buster gate array, assisted by a very high speed PAL and numerous TTL buffer chips for bus buffering, isolation, and multiplexing. The Amiga 4000 implementation was fundamentally the same, but integrated a second gate-array to replace the TTL buffers. The Buster chip provided bus arbitration, translation between the MC68030 bus protocols and either Zorro II or Zorro III bus cycles, and a vectored interrupt mechanism, generally not used. Zorro II bus masters were legal bus hogs, but Zorro III devices were fairly arbitrated and had controller-limited bus tenure. Despite being a 32-bit bus, Zorro III used the same 100 way slot and edge connector as Zorro II. The extra address and data lines were provided by multiplexing some of the existing connections with the nature of the lines changing at different stages of the bus access cycle. However, the bus was not fully multiplexed; the lower 8-bits of address were available during data cycles, which allowed Zorro III to support a fast burst cycle in page-mode. Properly designed Zorro II expansion cards could coexist with Zorro III cards; it was not a requirement of a Zorro III bus master to support DMA access to Zorro II bus targets. Cards could detect a Zorro III vs. Zorro II backplane, allowing certain Zorro III cards to function when connected to the older Zorro II bus, though at Zorro II's reduced data rates. The Zorro III bus has a theoretical bandwidth of 150 MByte/s, based on an ideal Zorro III master and slave device running with minimum setup and hold times. The real transfer speed between the Amiga 3000/4000 implementation of Zorro III and a Zorro III card is somewhere around 13.5 MByte/s due to the limitations of the Buster chip. This was comparable to Intel's first PCI implementation, which peaked at 25 MByte/s. Zorro III was optimized for future single-chip implementations of the protocol, but the resources available at Commodore in 1990 limited the initial implementation. This is also the limiting factor with 3rd party Amiga PCI expansion boards like e.g. Elbox Mediator PCI or the Matay Prometheus PCI. DMA transfers between two Zorro III cards can be much faster.
Memory map
Physical
The physical connector is a standard 2,54 mm spaced card edge connector with 2 × 50 rows of pins. Power:
