Charge-induced voltage alteration


Charge-induced voltage alteration is a technique which uses a scanning electron microscope to locate open conductors on CMOS integrated circuits. This technique is used in semiconductor failure analysis.

Theory of operation

The scanning of an electron beam across the surface of the device may result in additional charge buildup on conductors which are disconnected from the remainder of the circuit. If a CMOS device is under active bias, the presence of open conductors may not prevent the circuit from operating at low clock frequencies as the result of quantum tunneling effects. By injecting charge into floating conductors that are operating in this tunneling mode, it is possible to produce additional loading which can be detected by monitoring the power supply current. These changes in supply current may be associated with the visual image of the device at the coordinates at which the change was detected. The result is a scanning electron microscope image which has an overlay of the floating conductors superimposed on it.