Computation of cyclic redundancy checks
Computation of a cyclic redundancy check is derived from the mathematics of polynomial division, modulo two. In practice, it resembles long division of the binary message string, with a fixed number of zeroes appended, by the "generator polynomial" string except that exclusive or operations replace subtractions. Division of this type is efficiently realised in hardware by a modified shift register, and in software by a series of equivalent algorithms, starting with simple code close to the mathematics and becoming faster through byte-wise parallelism and space–time tradeoffs.
s placed according to powers of x in the generator polynomial. The message stream may be any length. After it has been shifted through the register, followed by 8 zeroes, the result in the register is the checksum.
Various CRC standards extend the polynomial division algorithm by specifying an initial shift register value, a final exclusive OR step and, most critically, a bit ordering. As a result, the code seen in practice deviates confusingly from "pure" division, and the register may shift left or right.
Example
As an example of implementing polynomial division in hardware, suppose that we are trying to compute an 8-bit CRC of an 8-bit message made of the ASCII character "W", which is binary 010101112, decimal 8710, or hexadecimal 5716. For illustration, we will use the CRC-8-ATM polynomial. Writing the first bit transmitted on the left, this corresponds to the 9-bit string "100000111".The byte value 5716 can be transmitted in two different orders, depending on the bit ordering convention used. Each one generates a different message polynomial. Msbit-first, this is = 01010111, while lsbit-first, it is = 11101010. These can then be multiplied by to produce two 16-bit message polynomials.
Computing the remainder then consists of subtracting multiples of the generator polynomial. This is just like decimal long division, but even simpler because the only possible multiples at each step are 0 and 1, and the subtractions borrow "from infinity" instead of reducing the upper digits. Because we do not care about the quotient, there is no need to record it.
Observe that after each subtraction, the bits are divided into three groups: at the beginning, a group which is all zero; at the end, a group which is unchanged from the original; and a blue shaded group in the middle which is "interesting". The "interesting" group is 8 bits long, matching the degree of the polynomial. Every step, the appropriate multiple of the polynomial is subtracted to make the zero group one bit longer, and the unchanged group becomes one bit shorter, until only the final remainder is left.
In the msbit-first example, the remainder polynomial is. Converting to a hexadecimal number using the convention that the highest power of x is the msbit; this is A216. In the lsbit-first, the remainder is. Converting to hexadecimal using the convention that the highest power of x is the lsbit, this is 1916.
Implementation
Writing out the full message at each step, as done in the example above, is very tedious. Efficient implementationsuse an -bit shift register to hold only the interesting bits. Multiplying the polynomial by is equivalent to shifting the register by one place, as the coefficients do not change in value but only move up to the next term of the polynomial.
Here is a first draft of some pseudocode for computing an n-bit CRC. It uses a contrived composite data type for polynomials, where
x is not an integer variable, but a constructor generating a Polynomial object that can be added, multiplied and exponentiated. To xor two polynomials is to add them, modulo two; that is, to exclusive OR the coefficients of each matching term from both polynomials.function crc
Note that this example code avoids the need to specify a bit-ordering convention by not using bytes; the input
bitString is already in the form of a bit array, and the remainderPolynomial is manipulated in terms of polynomial operations; the multiplication by could be a left or right shift, and the addition of bitString is done to the coefficient, which could be the right or left end of the register.This code has two disadvantages. First, it actually requires an n+1-bit register to hold the
remainderPolynomial so that the coefficient can be tested. More significantly, it requires the bitString to be padded with n zero bits.The first problem can be solved by testing the coefficient of the
remainderPolynomial before it is multiplied by.The second problem could be solved by doing the last n iterations differently, but there is a more subtle optimization which is used universally, in both hardware and software implementations.
Because the XOR operation used to subtract the generator polynomial from the message is commutative and associative, it does not matter in what order the various inputs are combined into the
remainderPolynomial. And specifically, a given bit of the bitString does not need to be added to the remainderPolynomial until the very last instant when it is tested to determine whether to xor with the generatorPolynomial.This eliminates the need to preload the
remainderPolynomial with the first n bits of the message, as well:function crc
This is the standard bit-at-a-time hardware CRC implementation, and is well worthy of study; once you understand why this computes exactly the same result as the first version, the remaining optimizations are quite straightforward. If
remainderPolynomial is only n bits long, then the coefficients of it and of generatorPolynomial are simply discarded. This is the reason that you will usually see CRC polynomials written in binary with the leading coefficient omitted.In software, it is convenient to note that while one may delay the
xor of each bit until the very last moment, it is also possible to do it earlier. It is usually convenient to perform the xor a byte at a time, even in a bit-at-a-time implementation like this:function crc
This is usually the most compact software implementation, used in microcontrollers when space is at a premium over speed.
Bit ordering (endianness)
When implemented in bit serial hardware, the generator polynomial uniquely describes the bit assignment; the first bit transmitted is always the coefficient of the highest power of, and the last bits transmitted are the CRC remainder, starting with the coefficient of and ending with the coefficient of, a.k.a. the coefficient of 1.However, when bits are processed a byte at a time, such as when using parallel transmission, byte framing as in 8B/10B encoding or RS-232-style asynchronous serial communication, or when implementing a CRC in software, it is necessary to specify the bit ordering of the data; which bit in each byte is considered "first" and will be the coefficient of the higher power of.
If the data is destined for serial communication, it is best to use the bit ordering the data will ultimately be sent in. This is because a CRC's ability to detect burst errors is based on proximity in the message polynomial ; if adjacent polynomial terms are not transmitted sequentially, a physical error burst of one length may be seen as a longer burst due to the rearrangement of bits.
For example, both IEEE 802 and RS-232 standards specify least-significant bit first transmission, so a software CRC implementation to protect data sent across such a link should map the least significant bits in each byte to coefficients of the highest powers of. On the other hand, floppy disks and most hard drives write the most significant bit of each byte first.
The lsbit-first CRC is slightly simpler to implement in software, so is somewhat more commonly seen, but many programmers find the msbit-first bit ordering easier to follow. Thus, for example, the XMODEM-CRC extension, an early use of CRCs in software, uses an msbit-first CRC.
So far, the pseudocode has avoided specifying the ordering of bits within bytes by describing shifts in the pseudocode as multiplications by and writing explicit conversions from binary to polynomial form. In practice, the CRC is held in a standard binary register using a particular bit-ordering convention. In msbit-first form, the most significant binary bits will be sent first and so contain the higher-order polynomial coefficients, while in lsbit-first form, the least-significant binary bits contain the higher-order coefficients. The above pseudocode can be written in both forms. For concreteness, this uses the 16-bit CRC-16-CCITT polynomial :
// Most significant bit first
// x^16+x^12+x^5+1 = 0001 0000 0010 0001 = 0x1021
function crc
// Least significant bit first
// x^16+x^12+x^5+1 = 1000 0100 0000 1000 = 0x8408
function crc
Note that the lsbit-first form avoids the need to shift
string before the xor. In either case, be sure to transmit the bytes of the CRC in the order that matches your chosen bit-ordering convention.Multi-bit computation
Another common optimization uses a lookup table indexed by highest order coefficients ofrem to process more than one bit of dividend per iteration. Most commonly, a 256-entry lookup table is used, replacing the inner loop over j with:// Msbit-first
rem = xor big_endian_table xor rightShift )]
// Lsbit-first
rem = xor little_endian_table xor ]
One of the most commonly encountered CRC algorithms is known as CRC-32, used by Ethernet, FDDI, ZIP and other archive formats, and PNG image format. Its polynomial can be written msbit-first as 0x04C11DB7, or lsbit-first as 0xEDB88320. The W3C webpage on PNG includes an appendix with a short and simple table-driven implementation in C of CRC-32. You will note that the code corresponds to the lsbit-first byte-at-a-time pseudocode presented here, and the table is generated using the bit-at-a-time code.
Using a 256-entry table is usually most convenient, but other sizes can be used. In small microcontrollers, using a 16-entry table to process four bits at a time gives a useful speed improvement while keeping the table small. On computers with ample storage, a -entry table can be used to process 16 bits at a time.
Generating the tables
The software to generate the tables is so small and fast that it is usually faster to compute them on program startup than to load precomputed tables from storage. One popular technique is to use the bit-at-a-time code 256 times to generate the CRCs of the 256 possible 8-bit bytes. However, this can be optimized significantly by taking advantage of the property thattable table xor table. Only the table entries corresponding to powers of two need to be computed directly.In the following example code,
crc holds the value of table:big_endian_table := 0
crc := 0x8000 // Assuming a 16-bit polynomial
i := 1
do while i < 256
little_endian_table := 0
crc := 1;
i := 128
do while i > 0
In these code samples, the table index
i + j is equivalent to i xor j; you may use whichever form is more convenient.Byte-Slicing using multiple tables
Parallel computation without table
Parallel update for a byte or a word at a time can also be done explicitly, without a table. This is normally used in high-speed hardware implementations. For each bit an equation is solved after 8 bits have been shifted in. The following tables list the equations for some commonly used polynomials, using following symbols:| ci | CRC bit 7…0 before update |
| ri | CRC bit 7…0 after update |
| di | input data bit 7…0 |
| ei = di + ci | ep = e7 + e6 + … + e1 + e0 ' |
| si = di + ci+8 | sp = s7 + s6 + … + s1 + s0 ' |
| Polynomial: | × x ' | x8 + x5 + x4 + 1 ' |
| Coefficients: | 0x12 = ' | 0x8c ' |
r0 ← r1 ← r2 ← r3 ← r4 ← r5 ← r6 ← r7 ← | 0 e0 + e4 + e7 e1 + e5 e2 + e6 e3 + e7 + e0 + e4 + e7 e4 + e1 + e5 e5 + e2 + e6 e6 + e3 + e7 | e0 + e4 + e1 + e0 + e5 + e2 + e1 e1 + e5 + e2 + e1 + e6 + e3 + e2 + e0 e2 + e6 + e3 + e2 + e0 + e7 + e4 + e3 + e1 e3 + e0 + e7 + e4 + e3 + e1 e4 + e1 + e0 e5 + e2 + e1 e6 + e3 + e2 + e0 e7 + e4 + e3 + e1 |
| C code fragments: | uint8_t c, d, e, f, r; … e = c ^ d; f = e ^ ^ ; r = ^ ; | uint8_t c, d, e, f, r; … e = c ^ d; f = e ^ ^ ^ ; r = f ^ ^ ; |
Two-step computation
As the CRC-32 polynomial has a large number of terms, when computing the remainder a byte at a time each bit depends on several bits of the previous iteration. In byte-parallel hardware implementations this calls for either multiple-input or cascaded XOR gates which increases propagation delay.To maximise computation speed, an intermediate remainder can be calculated by passing the message through a 123-bit shift register. The polynomial is a carefully selected multiple of the standard polynomial such that the terms are widely spaced, and no bit of the remainder is XORed more than once per byte iteration. Thus only two-input XOR gates, the fastest possible, are needed. Finally the intermediate remainder is divided by the standard polynomial in a second shift register to yield the CRC-32 remainder.
One-pass checking
When appending a CRC to a message, it is possible to detach the transmitted CRC, recompute it, and verify the recomputed value against the transmitted one. However, a simpler technique is commonlyused in hardware.
When the CRC is transmitted with the correct byte order, a receiver can compute an overall CRC, over the message and the CRC, and if they are correct, the result will be zero. This possibility is the reason that most network protocols that include a CRC do so before the ending delimiter; it is not necessary to know whether the end of the packet is imminent to check the CRC.
CRC variants
In practice, most standards specify presetting the register to all-ones and inverting the CRC before transmission. This has no effect on the ability of a CRC to detect changed bits, but gives it the ability to notice bits that are added to the message.Preset to −1
The basic mathematics of a CRC accepts messages which, when interpreted as a polynomial, are a multiple of the CRC polynomial. If some leading 0 bits are prepended to such a message, they will not change its interpretation as a polynomial. This is equivalent to the fact that 0001 and 1 are the same number.But if the message being transmitted does care about leading 0 bits, the inability of the basic CRC algorithm to detect such a change is undesirable. If it is possible that a transmission error could add such bits, a simple solution is to start with the
rem shift register set to some non-zero value; for convenience, the all-ones value is typically used. This is mathematically equivalent to complementing the first n bits of the message, where n is the number of bits in the CRC register.This does not affect CRC generation and checking in any way, as long as both generator and checker use the same initial value. Any non-zero initial value will do, and a few standards specify unusual values, but the all-ones value is by far the most common. Note that a one-pass CRC generate/check will still produce a result of zero when the message is correct, regardless of the preset value.
Post-invert
The same sort of error can occur at the end of a message, albeit with a more limited set of messages. Appending 0 bits to a message is equivalent to multiplying its polynomial by x, and if it was previously a multiple of the CRC polynomial, the result of that multiplication will be, as well. This is equivalent to the fact that, since 726 is a multiple of 11, so is 7260.A similar solution can be applied at the end of the message, inverting the CRC register before it is appended to the message. Again, any non-zero change will do; inverting all the bits is simply the most common.
This has an effect on one-pass CRC checking: instead of producing a result of zero when the message is correct, it produces a fixed non-zero result. Once this constant has been obtained, it can be used directly to verify the correctness of any other message checked using the same CRC algorithm.