DDR5 SDRAM is the official abbreviation for Double Data Rate 5 Synchronous Dynamic Random-Access Memory. Compared to its predecessor DDR4 SDRAM, DDR5 is planned to reduce power consumption, while doubling bandwidth. The standard, originally targeted for 2018, was released on 14 July 2020. A new feature deemed Decision Feedback Equalization enables IO speed scalability for higher bandwidth and performance improvement. DDR5 supports more bandwidth of its predecessor, DDR4 with 4.8 gigabits per second possible — but not shipping at launch. Rambus announced a working DDR5 DIMM in September 2017. On November 15, 2018, SK Hynix announced completion of its first DDR5 RAM chip; it runs at 5200 MT/s at 1.1 volts. In February 2019, SK Hynix announced a 6400 MT/s chip, the highest speed officially allowed by the preliminary DDR5 standard. Some companies were planning to bring the first products to market by the end of 2019. The unrelated JEDEC standard LP-DDR5, intended for laptops and smartphones, was released in February 2019. Compared to DDR4, DDR5 further reduces memory voltage to 1.1 V, thus reducing power consumption. DDR5 modules can incorporate on-board voltage regulators in order to reach higher speeds; as this will increase cost it is expected to be implemented only on server-grade and possibly high-end consumer modules. DDR5 supports a speed of 51.2 GB/s per module and 2 memory channels per module. There is a general expectation that most use-cases which currently use DDR4 will eventually migrate to DDR5. To be usable in desktops and servers, the integrated memory controllers of e.g. Intel's and AMD's CPUs will have to support it; as of June 2020, there has not been any official announcements of support from either, but a leaked slide shows planned DDR5 support on Intel's 2021 Sapphire Rapids microarchitecture. According to AMD's Forrest Norrod, AMD's mid-2020 Zen 3 based third generation Epyc CPUs will still use DDR4. A leaked internal AMD roadmap is reported to show DDR5 support for 2022 Zen 4 CPUs and Zen 3+ APUs.
DIMMs versus memory chips
While previous SDRAM generations allowed unbuffered DIMMs which consisted of memory chips and passive wiring, DDR5 DIMMs require additional active circuitry, making the interface to the DIMM different from the interface to the RAM chips themselves. First of all, a power supply; DDR5 DIMMs are supplied with 5V power, and use on-board circuitry to convert to the lower voltage required by the memory chips. Final voltage regulation close to the point of use provides more stable power, and mirrors the development of voltage regulator modules for CPU power supplies. Second, all DDR5 DIMMs are registered; a "registered clock driver" chip converts a 7-bit-wide double data rate command/address bus to the DIMM to the 14-bit-wide single data rate command/address signals expected by the DRAM chips. Third, there are two independent channels per DIMM. While earlier SDRAM generations had one CA bus controlling 64 or 72 data lines, each DDR5 DIMM has two CA buses controlling 32 or 40 data lines each, for a total of 64 or 80 data lines. A 4-byte bus width times a minimum burst length of 16 provides a minimum access size of 64 bytes, which matches the cache line size used by x86 microprocessors.
Operation
Standard DDR5 memory speeds range fom 4800 to 6400 million transfers per second. Higher speeds may be added later, as happened with previous generations. Minimum burst length was doubled to 16, with the option of "burst chop" after 8 transfers. Compared to DDR4 SDRAM, the number of bank groups is increased to 8, with the same 4 banks per group, for a total of 32.
Command encoding
The command encoding was significantly rearranged, and takes inspiration from that of LP-DDR4; commands are sent across a 14-bit bus, and while some simple commands take one cycle, any which include an address use two cycles to include 28 bits of information. Also like LPDDR, the mode registers have been reduced to 8 bits each, while the number of them has been greatly increased.
