The DLX is a RISCprocessor architecturedesigned by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs, the two benchmark examples of RISC design. The DLX is essentially a cleaned up simplified MIPS CPU. The DLX has a simple 32-bit load/store architecture, somewhat unlike the modern MIPS CPU. As the DLX was intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses. There are two known implementations: ASPIDA and VAMP. The ASPIDA project resulted in a core with many nice features: it is open source, supports Wishbone, has an asynchronous design, supports multiple ISAs, and is ASIC proven. VAMP is a DLX-variant that was mathematically verified as part of Verisoft project. It was specified with PVS, implemented in Verilog, and runs on a XilinxFPGA. A full stack from compiler to kernel to TCP/IP was built on it.
History
In the original MIPS architecture one of the methods used to gain performance was to force all instructions to complete in one clock cycle. This forced compilers to insert "no-ops" in cases where the instruction would definitely take longer than one clock cycle. Thus input and output activities specifically forced this behaviour, leading to artificial program bloat. In general MIPS programs were forced to have a lot of wasteful NOP instructions, a behaviour that was an unintended consequence. The DLX architecture does not force single clock cycle execution, and is therefore immune to this problem. In the DLX design a more modern approach to handling long instructions was used: data-forwarding and instruction reordering. In this case the longer instructions are "stalled" in their functional units, and then re-inserted into the instruction stream when they can complete. Externally this design behaviour makes it appear as if execution had occurred linearly.
How it works
DLX instructions can be broken down into three types, R-type, I-type and J-type. R-type instructions are pure register instructions, with three register references contained in the 32-bit word. I-type instructions specify two registers, and use 16 bits to hold an immediate value. Finally J-type instructions are jumps, containing a 26-bit address. Opcodes are 6 bits long, for a total of 64 possible basic instructions. To select one of 32 registers 5 bits are needed.
In the case of R-type instructions this means that only 21 bits of the 32-bit word are used, which allows the lower 6 bits to be used as "extended instructions".
The DLX can support more than 64 instructions, as long as those instructions work purely on registers. This quirk is useful for things like FPU support.
DLX vs MIPS
The DLX, like the MIPS design, bases its performance on the use of an instruction pipeline. In the DLX design this is a fairly simple one, "classic" RISC in concept. The pipeline contains five stages:
