Ian A. Young


Ian A. Young is an Intel executive. He was a manager of the design for an oscillator used in Intel microprocessors
Young has written 50 research papers, and has 71 patents
in switched capacitor circuits, DRAM, SRAM, BiCMOS, x86 clocking, Photonics and spintronics.

Biography

Born in Melbourne, Australia, Young received his bachelor's and master's degrees in electrical engineering from the University of Melbourne, Australia. He received his PhD in electrical engineering from the University of California, Berkeley in 1978, where he did research on MOSFET switched-capacitor filters.

Technical career

Early career, analog MOS integrated circuits and switched capacitor filters

Young obtained his PhD from University of California, Berkeley in 1978, working with David A. Hodges, developing the first switched MOS capacitor circuits which later developed into analogue MOS switched capacitor filters.

Intel BiCMOS for Logic and SRAM

Young started at Intel in 1983 with the development of circuits for the world's first 1 Mb DRAM in 1 μm CMOS in 1985, and first 64 K SRAM in 1 μm CMOS. This was also the first military qualified SRAM under the VHIC program. At 600 nanometre node, Intel adopted BiCMOS for logic requiring the development of a BiCMOS SRAM for cache and a new family of standard logic circuits.The BiCMOS logic family employed the npn devices in the pull-up path of the BiCMOS gate, to form a low power CMOS logic family with high capacitive drive capability. Intel's BiCMOS technology was enabled by an innovative triple diffused npn transistor. This led to a highly manufacturable low cost process due to minimum number of additional process steps. In contrast, other companies employed BiCMOS to implement emitter-coupled logic for microprocessors, which consumed much more power. The BiCMOS circuits were developed for the Pentium processor family and its follow-on generations, Pentium Pro, Pentium II processor family.

Pentium era and clock scaling

Young developed the original Phase Locked Loop based clocking circuit in a microprocessor while working on the 50 MHz Intel 80486 processor design. He subsequently developed the core PLL clocking circuit building blocks used in each generation of Intel microprocessors through the 0.13 μm 3.2 GHz Pentium 4. The successful introduction of GHz clocking contributed to massive improvements in computing power.

The integration of an on-chip PLL enabled the clock rates to exceed the off chip interconnect I/O rate in DX2. This led to the integration of an on-chip cache, paving the path for the first microprocessor with 1 million transistors.
The clock rate scaling ushered by Intel and AMD ended as the thermal power dissipation of processors reached 100 W/cm^2. By the end of the race for clock speed, the clock rates had increased by a factor of more than 50. Intel subsequently shifted to multi-core era with modified Intel Core architecture and concurrent improvements in cache sizes to take advantage of the continued success of Moore's law.

Interconnects and photonics

In 2001, as single end signalled aluminium interconnects reached the technology scaling limits, Young and co-workers quantified the migration to repeated electrical interconnects for mainstream microprocessors.

Beyond CMOS computing

He oversaw Dr. Dmitri Nikonov et al. for a uniform bench marking to identify the technology options in spintronics, tunnel junction and photonics devices.
He is also the founding editor-in-chief of IEEE Journal of Exploratory Solid State Computational Devices.

Awards and honours