Intel 5 Series


Intel 5 Series is a computing architecture introduced in 2008 that improves the efficiency and balances the use of communication channels in the motherboard. The architecture consists primarily of a central processing unit and a single chipset. All motherboard communications and activities circle around these two devices.
The architecture is a product of adjustments made to the Intel 4 Series to deliver higher performance motherboards while maintaining efficiency and low power. The changes revolve around chipset and processor design, in conjunction with a rearrangement of functions and controllers. The result is the first major change in many years of computing.

Design concept

The concept of the architecture was to improve motherboard mechanics to keep pace with the CPU as it gained more speed and multiplied in number of cores. In the previous architecture, the CPU was communicating heavily with the motherboard's central component, the Northbridge chipset, as it was the intermediary between the CPU, memory, and, in most cases, graphics card. The CPU would communicate with the Northbridge chipset when it needed data from the memory or when it needed to output graphics to the display. This arrangement caused the communication channel known as the front-side bus to be heavily used. It was not long till either the FSB would reach full capacity or operate inefficiently with more cores. With the memory controller and/or graphics core moved into the processor, the reliance of separate motherboard chipsets for these functions are reduced.

Ibex Peak

The Ibex Peak chipset includes only Platform Controller Hub per model, which provides peripheral connections, and display controllers for CPU with integrated graphics via Flexible Display Interface. Additionally, the PCH is connected to the CPU via Direct Media Interface.
Taking advantage of Intel Nehalem CPUs with integrated graphics and PCI Express ports, the Intel Management Engine and a display controller for integrated graphics, once housed in north bridge, are moved into the Platform Controller Hub. The I/O Controller Hub function is integrated into the PCH, removing the need for separate north bridge and south bridge.
ChipsetCode NamesSpec NumberPart numbersRelease DateBus InterfaceLink SpeedPCI Express lanesPCISATAUSBFDI supportTDP
ChipsetCode NamesSpec NumberPart numbersRelease DateBus InterfaceLink SpeedPCI Express lanesPCI3 Gbit/sv2.0FDI supportTDP
'Ibex PeakSLGZXBD82H55 Jan 2010DMI2 GB/s6 PCIe 2.0 at 2.5 GT/srowspan="4" 6 ports12 ports5.2 W
'Ibex PeakSLH24 ,
SLGWV 		BD82P55 Sep 2009DMI2 GB/s8 PCIe 2.0 at 2.5 GT/s14 ports6 ports4.7 W-
'Ibex PeakSLGZLBD82H57 Jan 2010DMI2 GB/s8 PCIe 2.0 at 2.5 GT/s14 ports6 portsrowspan="2" 5.2 W-
'Ibex PeakSLGZWBD82Q57 Jan 2010DMI2 GB/s8 PCIe 2.0 at 2.5 GT/s14 ports6 ports5.1 W--

ModelTop marking
PM55 ExpressBD82PM55
QM57 ExpressBD82QM57
HM55 ExpressBD82HM55
HM57 ExpressBD82HM57
QS57 ExpressBD82QS57

Tylersburg

The Tylersburg family of chipsets is for Socket LGA 1366 supporting CPUs with triple channel memory controllers. Unlike the Ibex Peak chipsets, The Tylersburg family of chipsets do not include the PCH, and the I/O Hub mainly provides extra PCI Express 2.0 ports. Peripheral connections are provided by I/O Controller Hub connected to the DMI interface. Intel 5 series IOH support ICH10, while Intel 5500 Series IOH support ICH9 or ICH10.

Single socket Nehalem">Nehalem (microarchitecture)">Nehalem-based chipset

The Nehalem-based Xeons for dual-socket systems, initially launched as the Xeon 55xx series, feature a very different system structure: the memory controllers are on the CPU, and the CPUs can communicate with one another as peers without going via the chipset. This means that the 5500 and 5520 chipsets are essentially QPI to PCI Express interfaces; the 5520 is more intended for graphical workstations and the 5500 for servers that do not need vast amounts of PCI Express connectivity
Launch nameCodenameQPI portsQPI speedFast I/OIOCHOther featuresTop marking
Tylersburg-24S,
Tylersburg-24D		1,
2		4.8, 5.86 or 6.4 GT/s1 ×16 PCIe Gen 2, 2 ×4 PCIe Gen 1 to talk to southbridgeICH10 Integrated Management Engine with its own 100 Mbit EthernetAC5500 SLGMT 901036, AC5500 SLH3N 904728
Tylersburg-36S,
Tylersburg-36D		1,
2		4.8, 5.86 or 6.4 GT/s2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridgeICH10 Integrated Management Engine with its own 100 Mbit EthernetAC5520 SLGMU 901037, AC5520 SLH3P 904729

Ibex Peak

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