Intel Memory Model


In computing, Intel Memory Model refers to a set of six different memory models of the x86 CPU operating in real mode which control how the segment registers are used and the default size of pointers.

Memory segmentation

Four registers are used to refer to four segments on the 16-bit x86 segmented memory architecture. DS, CS, SS, and ES. Another 16-bit register can act as an offset into a given segment, and so a logical address on this platform is written segment:offset, typically in hexadecimal notation. In real mode, in order to calculate the physical address of a byte of memory, the hardware shifts the contents of the appropriate segment register 4 bits left, and then adds the offset.
For example, the logical address 7522:F139 yields the 20-bit physical address:
Note that this process leads to aliasing of memory, such that any given physical address has up to 4096 corresponding logical addresses. This complicates the comparison of pointers to different segments.

Pointer sizes

formats are known as near, far, or huge.

mov bx, word
mov ax, word
mov dx, word


les bx,dword
mov ax,word
mov dx,word


les bx,dword
mov ax,word
add bx,2
test bx,0xfff0
jz lbl
sub bx,0x10
mov dx,es
inc dx
mov es,dx
lbl:
mov dx,word

Memory models

The memory models are:

Other platforms

In protected mode a segment cannot be both writable and executable. Therefore, when implementing the Tiny memory model the code segment register must point to the same physical address and have the same limit as the data segment register. This defeated one of the features of the 80286, which makes sure data segments are never executable and code segments are never writable. However, on the 80386, with its paged memory management unit it is possible to protect individual memory pages against writing.
Memory models are not limited to 16-bit programs. It is possible to use segmentation in 32-bit protected mode as well and there exist C language compilers which support that. However segmentation in 32-bit mode does not allow to access a larger address space than what a single segment would cover, unless some segments are not always present in memory and the linear address space is just used as a cache over a larger segmented virtual space. It allows better protection for access to various objects, and is therefore only used in specialized applications, like telecommunications software. Technically, the "flat" 32-bit address space is a "tiny" memory model for the segmented address space. Under both reigns all four segment registers contain one and the same value.

x86-64

On the x86-64 platform, a total of seven memory models exist, as the majority of symbol references are only 32 bits wide, and if the addresses are known at link time. This does not affect the pointers used, which are always flat 64-bit pointers, but only how values that have to be accessed via symbols can be placed.