List of Intel microprocessors

Latest

10th generation Core/[Comet Lake]/Ice Lake">Ice Lake (microarchitecture)">Ice Lake

9th generation Core/Coffee Lake processors|Coffee Lake Refreshed]]

8th generation Core/[Coffee Lake]/[Kaby Lake Refresh]/Whiskey Lake">Whiskey Lake (microarchitecture)">Whiskey Lake

Desktop

Mobile

7th generation Core/[Kaby Lake]/Skylake (X-series Processors)">Skylake-X">Skylake (X-series Processors)/[Apollo Lake]

Desktop version

Mobile version

All processors

The [4-bit] processors

[Intel 4004]

• Clock rate 740 kHz
• 0.07 MIPS
• Bus width: 4 bits
• PMOS
• 2,300 transistors at 10 μm
• Addressable memory 640 bytes
• Program memory 4 KB
• Originally designed to be used in Busicom calculator

• 4004 – CPU
• 4001 – ROM & 4-bit Port
• 4002 – RAM & 4-bit Port
• 4003 – 10-bit Shift Register
• 4008 – Memory+I/O Interface
• 4009 – Memory+I/O Interface
• Introduced November 15, 1971
• 4211 – General Purpose Byte I/O Port
• 4265 – Programmable General Purpose I/O Device
• 4269 – Programmable Keyboard Display Device
• 4289 – Standard Memory Interface for MCS-4/40
• 4308 – 8192-bit ROM w/ 4-bit I/O Ports
• 4316 – 16384-bit Static ROM
• 4702 – 2048-bit EPROM
• 4801 – 5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A
• Introduced 1971

[Intel 4040]

• Introduced in 1974 by Intel
• Clock speed was 740 kHz
• 3,000 transistors
• Interrupt features were available
• Programmable memory size: 8 KB
• 640 bytes of data memory
• 24-pin DIP

  The [8-bit] processors

[8008]

• Introduced April 1, 1972
• Clock rate 500 kHz
• 0.05 MIPS
• Bus width: 8 bits
• Enhancement load PMOS logic
• 3,500 transistors at 10 μm
• Addressable memory 16 KB
• Typical in early 8-bit microcomputers, dumb terminals, general calculators, bottling machines
• Developed in tandem with 4004
• Originally intended for use in the Datapoint 2200 microcomputer
• Key volume deployment in Texas Instruments 742 microcomputer in >3,000 Ford dealerships

[8080]

• Introduced April 1, 1974
• Clock rate 2 MHz
• 0.29 MIPS
• Data bus width: 8 bits, address bus: 16 bits
• Enhancement load NMOS logic
• 4,500 transistors at 6 μm
• Assembly language downward compatible with 8008
• Addressable memory 64 KB
• Up to 10× the performance of the 8008
• Used in e.g. the Altair 8800, traffic light controller, cruise missile
• Required six support chips versus 20 for the 8008

[8085]

• Introduced March 1976
• Clock rate 3 MHz
• 0.37 MIPS
• Data bus width: 8 bits, address bus: 16 bits
• Depletion load NMOS logic
• 6,500 transistors at 3 μm
• Binary compatible downward with the 8080
• Used in Toledo scales. Also used as a computer peripheral controller – modems, hard disks, printers, etc.
• CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable

  Microcontrollers

[Intel 8048]

• Single accumulator Harvard architecture

• 8020 – Single-Component 8-bit Microcontroller
• 8021 – Single-Component 8-bit Microcontroller
• 8022 – Single-Component 8-bit Microcontroller With On-Chip A/D Converter
• 8035 – Single-Component 8-bit Microcontroller
• 8039 – Single-Component 8-bit Microcontroller
• 8040 – Single-Component 8-bit Microcontroller
• 8041 – Universal Peripheral Interface 8-bit Slave Microcontroller
• 8641 – Universal Peripheral Interface 8-bit Slave Microcontroller
• 8741 – Universal Peripheral Interface 8-bit Slave Microcontroller
• 8042 – Universal Peripheral Interface 8-bit Slave Microcontroller
• 8742 – Universal Peripheral Interface 8-bit Slave Microcontroller
• 8243 – Input/Output Expander
• 8244 – General Purpose Graphics Display Device
• 8245 – General Purpose Graphics Display Device
• 8048 – Single-Component 8-bit Microcontroller
• 8048 – Single-Component 8-bit Microcontroller
• 8748 – Single-Component 8-bit Microcontroller
• 8048 – Single-Component 8-bit Microcontroller
• 8049 – Single-Component 8-bit Microcontroller
• 8749 – Single-Component 8-bit Microcontroller
• 8050 – Single-Component 8-bit Microcontroller

[Intel 8051]

• Single accumulator Harvard architecture

• 8031 – 8-bit Control-Oriented Microcontroller
• 8032 – 8-bit Control-Oriented Microcontroller
• 8044 – High Performance 8-bit Microcontroller
• 8344 – High Performance 8-bit Microcontroller
• 8744 – High Performance 8-bit Microcontroller
• 8051 – 8-bit Control-Oriented Microcontroller
• 8052 – 8-bit Control-Oriented Microcontroller
• 8054 – 8-bit Control-Oriented Microcontroller
• 8058 – 8-bit Control-Oriented Microcontroller
• 8351 – 8-bit Control-Oriented Microcontroller
• 8352 – 8-bit Control-Oriented Microcontroller
• 8354 – 8-bit Control-Oriented Microcontroller
• 8358 – 8-bit Control-Oriented Microcontroller
• 8751 – 8-bit Control-Oriented Microcontroller
• 8752 – 8-bit Control-Oriented Microcontroller
• 8754 – 8-bit Control-Oriented Microcontroller
• 8758 – 8-bit Control-Oriented Microcontroller

  [Intel 80151]

• Single accumulator Harvard architecture

• 80151 – High Performance 8-bit Control-Oriented Microcontroller
• 83151 – High Performance 8-bit Control-Oriented Microcontroller
• 87151 – High Performance 8-bit Control-Oriented Microcontroller
• 80152 – High Performance 8-bit Control-Oriented Microcontroller
• 83152 – High Performance 8-bit Control-Oriented Microcontroller

  [Intel 80251]

• Single accumulator Harvard architecture

• 80251 – 8/16/32-bit Microcontroller
• 80252 – 8/16/32-bit Microcontroller
• 80452 – 8/16/32-bit Microcontroller
• 83251 – 8/16/32-bit Microcontroller
• 87251 – 8/16/32-bit Microcontroller
• 87253 – 8/16/32-bit Microcontroller

  MCS-96">Intel MCS-96">MCS-96 family

• 8061 - 16-bit Microcontroller
• 8094 – 16-bit Microcontroller
• 8095 – 16-bit Microcontroller
• 8096 – 16-bit Microcontroller
• 8097 – 16-bit Microcontroller
• 8394 – 16-bit Microcontroller
• 8395 – 16-bit Microcontroller
• 8396 – 16-bit Microcontroller
• 8397 – 16-bit Microcontroller
• 8794 – 16-bit Microcontroller
• 8795 – 16-bit Microcontroller
• 8796 – 16-bit Microcontroller
• 8797 – 16-bit Microcontroller
• 8098 – 16-bit Microcontroller
• 8398 – 16-bit Microcontroller
• 8798 – 16-bit Microcontroller
• 80196 – 16-bit Microcontroller
• 83196 – 16-bit Microcontroller
• 87196 – 16-bit Microcontroller
• 80296 – 16-bit Microcontroller

  The bit-slice">Bit slicing">bit-slice processor

3000 Family

• 3001 – Microcontrol Unit
• 3002 – 2-bit Arithmetic Logic Unit slice
• 3003 – Look-ahead Carry Generator
• 3205 – High-performance 1 of 8 Binary Decoder
• 3207 – Quad Bipolar-to-MOS Level Shifter and Driver
• 3208 – Hex Sense Amp and Latch for MOS Memories
• 3210 – TTL-to-MOS Level Shifter and High Voltage Clock Driver
• 3211 – ECL-to-MOS Level Shifter and High Voltage Clock Driver
• 3212 – Multimode Latch Buffer
• 3214 – Interrupt Control Unit
• 3216 – Parallel, Inverting Bi-Directional Bus Driver
• 3222 – Refresh Controller for 4K NMOS DRAMs
• 3226 – Parallel, Inverting Bi-Directional Bus Driver
• 3232 – Address Multiplexer and Refresh Counter for 4K DRAMs
• 3242 – Address Multiplexer and Refresh Counter for 16K DRAMs
• 3245 – Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
• 3246 – Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
• 3404 – High-performance 6-bit Latch
• 3408 – Hex Sense Amp and Latch for MOS Memories
• 3505 – Next generation processor

The [16-bit] processors: MCS-86 family

8086">Intel 8086">8086

• Introduced June 8, 1978
• Clock rates:
• * 5 MHz, 0.33 MIPS
• * 8 MHz, 0.66 MIPS
• * 10 MHz, 0.75 MIPS
• The memory is divided into odd and even banks. It accesses both banks concurrently to read 16 bits of data in one clock cycle
• Data bus width: 16 bits, address bus: 20 bits
• 29,000 transistors at 3 μm
• Addressable memory 1 megabyte
• Up to 10× the performance of 8080
• First used in the Compaq Deskpro IBM PC-compatible computers. Later used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible
• Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.
• The first x86 CPU
• Later renamed the iAPX 86

8088">Intel 8088">8088

• Introduced June 1, 1979
• Clock rates:
• * 4.77 MHz, 0.33 MIPS
• * 8 MHz, 0.66 MIPS
• 16-bit internal architecture
• External data bus width: 8 bits, address bus: 20 bits
• 29,000 transistors at 3 μm
• Addressable memory 1 megabyte
• Identical to 8086 except for its 8-bit external bus ; identical Execution Unit, different Bus Interface Unit
• Used in IBM PC and PC-XT and compatibles
• Later renamed the iAPX 88

80186">Intel 80186">80186

• Introduced 1982
• Clock rates
• * 6 MHz, > 1 MIPS
• 55,000 transistors
• Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor
• Added a few opcodes and exceptions to the 8086 design, otherwise identical instruction set to 8086 and 8088
• * BOUND, ENTER, LEAVE
• * INS, OUTS
• * IMUL imm, PUSH imm, PUSHA, POPA
• * RCL/RCR/ROL/ROR/SHL/SHR/SAL/SAR reg,imm
• Address calculation and shift operations are faster than 8086
• Used mostly in embedded applications – controllers, point-of-sale systems, terminals, and the like
• Used in several non-PC compatible DOS computers including RM Nimbus, Tandy 2000, and CP/M 86 Televideo PM16 server
• Later renamed to iAPX 186

  80188">Intel 80188">80188

• A version of the 80186 with an 8-bit external data bus
• Later renamed the iAPX 188

80286">Intel 80286">80286

• Introduced February 2, 1982
• Clock rates:
• * 6 MHz, 0.9 MIPS
• * 8 MHz, 10 MHz, 1.5 MIPS
• * 12.5 MHz, 2.66 MIPS
• * 16 MHz, 20 MHz and 25 MHz available.
• Data bus width: 16 bits, address bus: 24 bits
• Included memory protection hardware to support multitasking operating systems with per-process address space.
• 134,000 transistors at 1.5 μm
• Addressable memory 16 MB
• Added protected-mode features to 8086 with essentially the same instruction set
• 3–6× the performance of the 8086
• Widely used in IBM PC AT and AT clones contemporary to it

  [32-bit] processors: the non-x86 microprocessors

iAPX 432">Intel iAPX 432">iAPX 432

• Introduced January 1, 1981 as Intel's first 32-bit microprocessor
• Multi-chip CPU
• Object/capability architecture
• Microcoded operating system primitives
• One terabyte virtual address space
• Hardware support for fault tolerance
• Two-chip General Data Processor, consists of 43201 and 43202
• 43203 Interface Processor interfaces to I/O subsystem
• 43204 Bus Interface Unit simplifies building multiprocessor systems
• 43205 Memory Control Unit
• Architecture and execution unit internal data base paths: 32 bits
• Clock rates:
• * 5 MHz
• * 7 MHz
• * 8 MHz

  i960 a.k.a. 80960">Intel i960">i960 a.k.a. 80960

• Introduced April 5, 1988
• RISC-like 32-bit architecture
• Predominantly used in embedded systems
• Evolved from the capability processor developed for the BiiN joint venture with Siemens
• Many variants identified by two-letter suffixes

  i860 a.k.a. 80860">Intel i860">i860 a.k.a. 80860

• Introduced February 26, 1989
• RISC 32/64-bit architecture, with floating point pipeline characteristics very visible to programmer
• Used in the Intel iPSC/860 Hypercube parallel supercomputer
• Mid-life kicker in the i870 processor
• Used in the Intel Delta massively parallel supercomputer prototype, emplaced at California Institute of Technology
• Used in the Intel Paragon massively parallel supercomputer, emplaced at Sandia National Laboratory

  [XScale]

• Introduced August 23, 2000
• 32-bit RISC microprocessor based on the ARM architecture
• Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors

  [32-bit] processors: the 80386 range

80386DX">Intel 80386">80386DX

• Introduced October 17, 1985
• Clock rates:
• * 16 MHz, 5 MIPS
• * 20 MHz, 6 to 7 MIPS, introduced February 16, 1987
• * 25 MHz, 7.5 MIPS, introduced April 4, 1988
• * 33 MHz, 9.9 MIPS, introduced April 10, 1989
• Data bus width: 32 bits, address bus: 32 bits
• 275,000 transistors at 1 μm
• Addressable memory 4 GB
• Virtual memory 64 TB
• First x86 chip to handle 32-bit data sets
• Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required at the time by Xenix and Unix. This memory capability spurred the development and availability of OS/2 and is a fundamental requirement for modern operating systems like Linux, Windows, and macOS
• First used by Compaq in the Deskpro 386. Used in desktop computing
• Unlike the DX naming convention of the 486 chips, it had no math co-processor
• Later renamed Intel386 DX

  80386SX">Intel 80386SX">80386SX

• Introduced June 16, 1988
• Clock rates:
• * 16 MHz, 2.5 MIPS
• * 20 MHz, 3.1 MIPS, introduced January 25, 1989
• * 25 MHz, 3.9 MIPS, introduced January 25, 1989
• * 33 MHz, 5.1 MIPS, introduced October 26, 1992
• 32-bit internal architecture
• External data bus width: 16 bits
• External address bus width: 24 bits
• 275,000 transistors at 1 μm
• Addressable memory 16 MB
• Virtual memory 64 TB
• Narrower buses enable low-cost 32-bit processing
• Used in entry-level desktop and portable computing
• No math co-processor
• No commercial software used protected mode or virtual storage for many years
• Later renamed Intel386 SX

  80376">Intel 80376">80376

• Introduced January 16, 1989; discontinued June 15, 2001
• Variant of 386SX intended for embedded systems
• No "real mode", starts up directly in "protected mode"
• Replaced by much more successful [|80386EX] from 1994

  80386SL">Intel 80386SL">80386SL

• Introduced October 15, 1990
• Clock rates:
• * 20 MHz, 4.21 MIPS
• * 25 MHz, 5.3 MIPS, introduced September 30, 1991
• 32-bit internal architecture
• External bus width: 16 bits
• 855,000 transistors at 1 μm
• Addressable memory 4 GB
• Virtual memory 64 TB
• First chip specifically made for portable computers because of low power consumption of chip
• Highly integrated, includes cache, bus, and memory controllers

80386EX">Intel 80386EX">80386EX

• Introduced August 1994
• Variant of 80386SX intended for embedded systems
• Static core, i.e. may run as slowly as desired, down to full halt
• On-chip peripherals:
• * Clock and power management
• * Timers/counters
• * Watchdog timer
• * Serial I/O units and parallel I/O
• * DMA
• * RAM refresh
• * JTAG test logic
• Significantly more successful than the 80376
• Used aboard several orbiting satellites and microsatellites
• Used in NASA's FlightLinux project

  32-bit processors: the 80486 range

80486DX">Intel 80486DX">80486DX

• Introduced April 10, 1989
• Clock rates:
• * 25 MHz, 20 MIPS
• * 33 MHz, 27 MIPS, introduced May 7, 1990
• * 50 MHz, 41 MIPS, introduced June 24, 1991
• Bus width: 32 bits
• 1.2 million transistors at 1 μm; the 50 MHz was at 0.8 μm
• Addressable memory 4 GB
• Virtual memory 64 TB
• Level 1 cache of 8 KB on chip
• Math coprocessor on chip
• 50× performance of the 8088
• Officially named Intel486 DX
• Used in Desktop computing and servers
• Family 4 model 1

80486SX">Intel 80486SX">80486SX

• Introduced April 22, 1991
• Clock rates:
• * 16 MHz, 13 MIPS
• * 20 MHz, 16.5 MIPS, introduced September 16, 1991
• * 25 MHz, 20 MIPS, introduced September 16, 1991
• * 33 MHz, 27 MIPS, introduced September 21, 1992
• Bus width: 32 bits
• 1.185 million transistors at 1 μm and 900,000 at 0.8 μm
• Addressable memory 4 GB
• Virtual memory 64 TB
• Identical in design to 486DX but without a math coprocessor. The first version was an 80486DX with disabled math coprocessor in the chip and different pin configuration. If the user needed math coprocessor capabilities, he must add 487SX which was actually a 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 effectively turned on
• Officially named Intel486 SX
• Used in low-cost entry to 486 CPU desktop computing, as well as extensively in low cost mobile computing
• Upgradable with the Intel OverDrive processor
• Family 4 model 2

80486DX2">Intel 80486DX2">80486DX2

• Introduced March 3, 1992
• Runs at twice the speed of the external bus
• Fits in Socket 3
• Clock rates:
• * 40 MHz
• * 50 MHz
• * 66 MHz
• Officially named Intel486 DX2
• Family 4 model 3

80486SL">Intel 80486SL">80486SL

• Introduced November 9, 1992
• Clock rates:
• * 20 MHz, 15.4 MIPS
• * 25 MHz, 19 MIPS
• * 33 MHz, 25 MIPS
• Bus width: 32 bits
• 1.4 million transistors at 0.8 μm
• Addressable memory 4 GB
• Virtual memory 64 TB
• Officially named Intel486 SL
• Used in notebook computers
• Family 4 model 4

80486DX4">Intel 80486DX4">80486DX4

• Introduced March 7, 1994
• Clock rates:
• * 75 MHz, 53 MIPS
• * 100 MHz, 70.7 MIPS
• 1.6 million transistors at 0.6 μm
• Bus width: 32 bits
• Addressable memory 4 GB
• Virtual memory 64 TB
• Socket 3 168 pin PGA Package, or 208 sq. ftP Package
• Officially named Intel486 DX4
• Used in high performance entry-level desktops and value notebooks
• Family 4 model 8

  32-bit processors: P5">P5 (microarchitecture)">P5 microarchitecture

Original Pentium">Pentium (brand)">Pentium

• Bus width: 64 bits
• System bus clock rate 60 or 66 MHz
• Address bus: 32 bits
• Addressable memory 4 GB
• Virtual Memory 64 TB
• Superscalar architecture
• Runs on 3.3 Volts
• Used in desktops
• 8 KB of instruction cache
• 8 KB of data cache
• P5 – 0.8 μm process technology
• * Introduced March 22, 1993
• * 3.1 million transistors
• * The only Pentium to run on 5 Volts
• * Socket 4 273 pin PGA Package
• * Package dimensions 2.16″ × 2.16″
• * Family 5 model 1
• * Variants
• ** 60 MHz, 100 MIPS
• ** 66 MHz, 112 MIPS
• P54 – 0.6 μm process technology
• * Socket 5 296/320 pin PGA package
• * 3.2 million transistors
• * Variants
• ** 75 MHz, 126.5 MIPS
• *** Introduced October 10, 1994
• ** 90, 100 MHz, 149.8 and 166.3 MIPS respectively
• *** Introduced March 7, 1994
• P54CQS – 0.35 μm process technology
• * Socket 5 296/320 pin PGA package
• * 3.2 million transistors
• * Variants
• ** 120 MHz, 203 MIPS
• *** Introduced March 27, 1995
• P54CS – 0.35 μm process technology
• * 3.3 million transistors
• * 90 mm² die size
• * Family 5 model 2
• * Variants
• * Socket 5 296/320 pin PGA package
• ** 133 MHz, 218.9 MIPS
• *** Introduced June 12, 1995
• ** 150, 166 MHz, 230 and 247 MIPS respectively
• *** Introduced January 4, 1996
• * Socket 7 296/321 pin PGA package
• ** 200 MHz, 270 MIPS
• *** Introduced June 10, 1996

[[Pentium MMX|Pentium with MMX Technology]]

• P55C – 0.35 μm process technology
• * Introduced January 8, 1997
• * Intel MMX support
• * Socket 7 296/321 pin PGA package
• * 16 KB L1 instruction cache
• * 16 KB L1 data cache
• * 4.5 million transistors
• * System bus clock rate 66 MHz
• * Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
• * Variants
• ** 166, 200 MHz introduced January 8, 1997
• ** 233 MHz introduced June 2, 1997
• ** 133 MHz
• ** 166, 266 MHz introduced January 12, 1998
• ** 200, 233 MHz introduced September 8, 1997
• ** 300 MHz introduced January 7, 1999

  [32-bit] processors: P6">P6 (microarchitecture)">P6/Pentium M">Pentium M (microarchitecture)">Pentium M microarchitecture

[Pentium Pro]

• Introduced November 1, 1995
• Multichip Module
• Precursor to Pentium II and III
• Primarily used in server systems
• Socket 8 processor package
• 5.5 million transistors
• Family 6 model 1
• 0.6 μm process technology
• * 16 KB L1 cache
• * 256 KB integrated L2 cache
• * 60 MHz system bus clock rate
• * Variants
• ** 150 MHz
• 0.35 μm process technology,
• * 5.5 million transistors
• * 512 KB or 256 KB integrated L2 cache
• * 60 or 66 MHz system bus clock rate
• * Variants
• ** 150 MHz introduced November 1, 1995
• ** 166 MHz introduced November 1, 1995
• ** 180 MHz introduced November 1, 1995
• ** 200 MHz introduced November 1, 1995
• ** 200 MHz introduced November 1, 1995
• ** 200 MHz introduced August 18, 1997

  [Pentium II]

• Introduced May 7, 1997
• Pentium Pro with MMX and improved 16-bit performance
• 242-pin Slot 1 processor package
• Voltage identification pins
• 7.5 million transistors
• 32 KB L1 cache
• 512 KB bandwidth external L2 cache
• The only Pentium II that did not have the L2 cache at bandwidth of the core was the Pentium II 450 PE.
• Klamath – 0.35 μm process technology
• * 66 MHz system bus clock rate
• * Family 6 model 3
• * Variants
• ** 233, 266, 300 MHz introduced May 7, 1997
• Deschutes – 0.25 μm process technology
• * Introduced January 26, 1998
• * 66 MHz system bus clock rate, 100 MHz system bus clock rate for all subsequent models
• * Family 6 model 5
• * Variants
• ** 333 MHz introduced January 26, 1998
• ** 350, 400 MHz introduced April 15, 1998
• ** 450 MHz introduced August 24, 1998
• ** 233, 266 MHz introduced April 2, 1998
• ** 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998
• ** 300 MHz introduced September 9, 1998
• ** 333 MHz introduced January 25, 1999

  [Celeron] (Pentium II-based)

• Covington – 0.25 μm process technology
• * Introduced April 15, 1998
• * 242-pin Slot 1 SEPP
• * 7.5 million transistors
• * 66 MHz system bus clock rate
• * Slot 1
• * 32 KB L1 cache
• * No L2 cache
• * Variants
• ** 266 MHz introduced April 15, 1998
• ** 300 MHz introduced June 9, 1998
• Mendocino – 0.25 μm process technology
• * Introduced August 24, 1998
• * 242-pin Slot 1 SEPP, Socket 370 PPGA package
• * 19 million transistors
• * 66 MHz system bus clock rate
• * Slot 1, Socket 370
• * 32 KB L1 cache
• * 128 KB integrated cache
• * Family 6 model 6
• * Variants
• ** 300, 333 MHz introduced August 24, 1998
• ** 366, 400 MHz introduced January 4, 1999
• ** 433 MHz introduced March 22, 1999
• ** 466 MHz
• ** 500 MHz introduced August 2, 1999
• ** 533 MHz introduced January 4, 2000
• ** 266 MHz
• ** 300 MHz
• ** 333 MHz introduced April 5, 1999
• ** 366 MHz
• ** 400 MHz
• ** 433 MHz
• ** 450 MHz introduced February 14, 2000
• ** 466 MHz
• ** 500 MHz introduced February 14, 2000

• Introduced June 29, 1998
• See [|main entry]

  [Pentium III]

• Katmai – 0.25 μm process technology
• * Introduced February 26, 1999
• * Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions
• * 9.5 million transistors
• * 512 KB bandwidth L2 External cache
• * 242-pin Slot 1 SECC2 processor package
• * System Bus clock rate 100 MHz, 133 MHz
• * Slot 1
• * Family 6 model 7
• * Variants
• ** 450, 500 MHz introduced February 26, 1999
• ** 550 MHz introduced May 17, 1999
• ** 600 MHz introduced August 2, 1999
• ** 533, 600 MHz introduced September 27, 1999
• Coppermine – 0.18 μm process technology
• * Introduced October 25, 1999
• * 28.1 million transistors
• * 256 KB Advanced Transfer L2 cache
• * 242-pin Slot-1 SECC2 processor package, 370-pin FC-PGA package
• * System Bus clock rate 100 MHz, 133 MHz
• * Slot 1, Socket 370
• * Family 6 model 8
• * Variants
• ** 500 MHz
• ** 533 MHz
• ** 550 MHz
• ** 600 MHz
• ** 600 MHz
• ** 650 MHz introduced October 25, 1999
• ** 667 MHz introduced October 25, 1999
• ** 700 MHz introduced October 25, 1999
• ** 733 MHz introduced October 25, 1999
• ** 750, 800 MHz introduced December 20, 1999
• ** 850 MHz introduced March 20, 2000
• ** 866 MHz introduced March 20, 2000
• ** 933 MHz introduced May 24, 2000
• ** 1000 MHz introduced March 8, 2000
• ** 1100 MHz
• ** 1133 MHz
• ** 400, 450, 500 MHz introduced October 25, 1999
• ** 600, 650 MHz introduced January 18, 2000
• ** 700 MHz introduced April 24, 2000
• ** 750 MHz introduced June 19, 2000
• ** 800, 850 MHz introduced September 25, 2000
• ** 900, 1000 MHz introduced March 19, 2001
• Tualatin – 0.13 μm process technology
• * Introduced July 2001
• * 28.1 million transistors
• * 32 KB L1 cache
• * 256 KB or 512 KB Advanced Transfer L2 cache
• * 370-pin FC-PGA2 package
• * 133 MHz system bus clock rate
• * Socket 370
• * Family 6 model 11
• * Variants
• ** 1133 MHz
• ** 1133 MHz
• ** 1200 MHz
• ** 1266 MHz
• ** 1333 MHz
• ** 1400 MHz

  Pentium II [Xeon] and Pentium III Xeon

• PII Xeon
• * Variants
• ** 400 MHz introduced June 29, 1998
• ** 450 MHz introduced October 6, 1998
• ** 450 MHz introduced January 5, 1999
• PIII Xeon
• * Introduced October 25, 1999
• * 9.5 million transistors at 0.25 μm or 28 million at 0.18 μm
• * L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache
• * Processor Package Style is Single Edge Contact Cartridge or SC330
• * System Bus clock rate 133 MHz or 100 MHz
• * System Bus width: 64 bits
• * Addressable memory: 64 GB
• * Used in two-way servers and workstations or 4- and 8-way servers
• * Family 6 model 10
• * Variants
• ** 500 MHz introduced March 17, 1999
• ** 550 MHz introduced August 23, 1999
• ** 600 MHz introduced October 25, 1999
• ** 667 MHz introduced October 25, 1999
• ** 733 MHz introduced October 25, 1999
• ** 800 MHz introduced January 12, 2000
• ** 866 MHz introduced April 10, 2000
• ** 933 MHz
• ** 1000 MHz introduced August 22, 2000
• ** 700 MHz introduced May 22, 2000

  [Celeron] (Pentium III Coppermine-based)

• Coppermine-128, 0.18 μm process technology
• * Introduced March, 2000
• * Streaming SIMD Extensions
• * Socket 370, FC-PGA processor package
• * 28.1 million transistors
• * 66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001
• * 32 KB L1 cache
• * 128 KB Advanced Transfer L2 cache
• * Family 6 model 8
• * Variants
• ** 533 MHz
• ** 566 MHz
• ** 600 MHz
• ** 633, 667, 700 MHz introduced June 26, 2000
• ** 733, 766 MHz introduced November 13, 2000
• ** 800 MHz introduced January 3, 2001
• ** 850 MHz introduced April 9, 2001
• ** 900 MHz introduced July 2, 2001
• ** 950, 1000, 1100 MHz introduced August 31, 2001
• ** 550 MHz
• ** 600, 650 MHz introduced June 19, 2000
• ** 700 MHz introduced September 25, 2000
• ** 750 MHz introduced March 19, 2001
• ** 800 MHz
• ** 850 MHz introduced July 2, 2001
• ** 600 MHz
• ** 500 MHz introduced January 30, 2001
• ** 600 MHz

• Introduced April 2000 – July 2002
• See main entries

  Pentium III Tualatin-based

• Tualatin – 0.13 μm process technology
• * 32 KB L1 cache
• * 512KB Advanced Transfer L2 cache
• * 133 MHz system bus clock rate
• * Socket 370
• * Variants
• ** 1.0 GHz
• ** 1.13 GHz
• ** 1.26 GHz
• ** 1.4 GHz

  [Celeron] (Pentium III Tualatin-based)

• Tualatin Celeron – 0.13 μm process technology
• * 32 KB L1 cache
• * 256 KB Advanced Transfer L2 cache
• * 100 MHz system bus clock rate
• * Socket 370
• * Family 6 model 11
• * Variants
• ** 1.0 GHz
• ** 1.1 GHz
• ** 1.2 GHz
• ** 1.3 GHz
• ** 1.4 GHz

  [Pentium M]

• Banias 0.13 μm process technology
• * Introduced March 2003
• * 64 KB L1 cache
• * 1 MB L2 cache
• * Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
• * 77 million transistors
• * Micro-FCPGA, Micro-FCBGA processor package
• * Heart of the Intel mobile Centrino system
• * 400 MHz Netburst-style system bus
• * Family 6 model 9
• * Variants
• ** 900 MHz
• ** 1.0 GHz
• ** 1.1 GHz
• ** 1.2 GHz
• ** 1.3 GHz
• ** 1.4 GHz
• ** 1.5 GHz
• ** 1.6 GHz
• ** 1.7 GHz
• Dothan 0.09 μm process technology
• * Introduced May 2004
• * 2 MB L2 cache
• * 140 million transistors
• * Revised data prefetch unit
• * 400 MHz Netburst-style system bus
• * 21W TDP
• * Family 6 model 13
• * Variants
• ** 1.00 GHz
• ** 1.10 GHz
• ** 1.20 GHz
• ** 1.30 GHz
• ** 1.40 GHz
• ** 1.50 GHz
• ** 1.60 GHz
• ** 1.40 GHz
• ** 1.50 GHz
• ** 1.60 GHz
• ** 1.70 GHz
• ** 1.80 GHz
• ** 2.00 GHz
• ** 2.10 GHz
• Dothan 533 0.09 μm process technology
• * Introduced Q1 2005
• * Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
• * Variants
• ** 1.60 GHz
• ** 1.73 GHz
• ** 1.86 GHz
• ** 2.00 GHz
• ** 2.13 GHz
• ** 2.26 GHz
• Stealey 0.09 μm process technology
• * Introduced Q2 2007
• * 512 KB L2, 3 W TDP
• * Variants
• ** 600 MHz
• ** 800 MHz

  Celeron M">Celeron">Celeron M

• Banias-512 0.13 μm process technology
• * Introduced March 2003
• * 64 KB L1 cache
• * 512 KB L2 cache
• * SSE2 SIMD instructions
• * No SpeedStep technology, is not part of the 'Centrino' package
• * Family 6 model 9
• * Variants
• ** 310 – 1.20 GHz
• ** 320 – 1.30 GHz
• ** 330 – 1.40 GHz
• ** 340 – 1.50 GHz
• Dothan-1024 90 nm process technology
• * 64 KB L1 cache
• * 1 MB L2 cache
• * SSE2 SIMD instructions
• * No SpeedStep technology, is not part of the 'Centrino' package
• * Variants
• ** 350 – 1.30 GHz
• ** 350J – 1.30 GHz, with Execute Disable bit
• ** 360 – 1.40 GHz
• ** 360J – 1.40 GHz, with Execute Disable bit
• ** 370 – 1.50 GHz, with Execute Disable bit
• *** Family 6, Model 13, Stepping 8
• ** 380 – 1.60 GHz, with Execute Disable bit
• ** 390 – 1.70 GHz, with Execute Disable bit
• Yonah-1024 65 nm process technology
• * 64 KB L1 cache
• * 1 MB L2 cache
• * SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
• * No SpeedStep technology, is not part of the 'Centrino' package
• * Variants
• ** 410 – 1.46 GHz
• ** 420 – 1.60 GHz,
• ** 423 – 1.06 GHz
• ** 430 – 1.73 GHz
• ** 440 – 1.86 GHz
• ** 443 – 1.20 GHz
• ** 450 – 2.00 GHz

  [Intel Core]

• Yonah 0.065 μm process technology
• * Introduced January 2006
• * 533/667 MHz front side bus
• * 2 MB L2 cache
• * SSE3 SIMD instructions
• * 31W TDP
• * Family 6, Model 14
• * Variants:
• ** Intel Core Duo T2700 2.33 GHz
• ** Intel Core Duo T2600 2.16 GHz
• ** Intel Core Duo T2500 2 GHz
• ** Intel Core Duo T2450 2 GHz
• ** Intel Core Duo T2400 1.83 GHz
• ** Intel Core Duo T2300 1.66 GHz
• ** Intel Core Duo T2050 1.6 GHz
• ** Intel Core Duo T2300e 1.66 GHz
• ** Intel Core Duo T2080 1.73 GHz
• ** Intel Core Duo L2500 1.83 GHz
• ** Intel Core Duo L2400 1.66 GHz
• ** Intel Core Duo L2300 1.5 GHz
• ** Intel Core Duo U2500 1.2 GHz
• ** Intel Core Solo T1350 1.86 GHz
• ** Intel Core Solo T1300 1.66 GHz
• ** Intel Core Solo T1200 1.5 GHz

  Dual-Core [Xeon] LV

• Sossaman 0.065 μm process technology
• * Introduced March 2006
• * Based on Yonah core, with SSE3 SIMD instructions
• * 667 MHz frontside bus
• * 2 MB Shared L2 cache
• * Variants
• ** 2.0 GHz

  32-bit processors: NetBurst">NetBurst (microarchitecture)">NetBurst microarchitecture

[Pentium 4]

• 0.18 μm process technology
• * Introduced November 20, 2000
• * L2 cache was 256 KB Advanced Transfer Cache
• * Processor Package Style was PGA423, PGA478
• * System Bus clock rate 400 MHz
• * SSE2 SIMD Extensions
• * 42 million transistors
• * Used in desktops and entry-level workstations
• 0.18 μm process technology
• * Introduced April 23, 2001
• * See the 1.4 and 1.5 chips for details
• 0.18 μm process technology
• * Introduced July 2, 2001
• * See 1.4 and 1.5 chips for details
• * Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
• * Power <1 watt in Battery Optimized Mode
• * Used in full-size and then light mobile PCs
• 0.18 μm process technology Willamette
• * Introduced August 27, 2001
• * See 1.4 and 1.5 chips for details
• Family 15 model 1
• Pentium 4
• * Introduced January 7, 2002
• Pentium 4
• * Introduced April 2, 2002
• 0.13 μm process technology Northwood A, 3.0
• * Improved branch prediction and other microcodes tweaks
• * 512 KB integrated L2 cache
• * 55 million transistors
• * 400 MHz system bus
• Family 15 model 2
• 0.13 μm process technology Northwood B
• * 533 MHz system bus.
• 0.13 μm process technology Northwood C
• * 800 MHz system bus
• * 6500 to 10,000 MIPS

• Introduced 2001
• See main entry

  [Xeon] (32-bit NetBurst)

• Official designation now Xeon, i.e. not "Pentium 4 Xeon"
• Xeon 1.4, 1.5, 1.7 GHz
• * Introduced May 21, 2001
• * L2 cache was 256 KB Advanced Transfer Cache
• * Processor Package Style was Organic Land Grid Array 603
• * System Bus clock rate 400 MHz
• * SSE2 SIMD Extensions
• * Used in high-performance and mid-range dual processor enabled workstations
• Xeon 2.0 GHz and up to 3.6 GHz
• * Introduced September 25, 2001

• Introduced July 2002
• See main entry

  Mobile Pentium 4-M

• 0.13 μm process technology
• 55 million transistors
• 512 KB L2 cache
• BUS a 400 MHz
• Supports up to 1 GB of DDR 266 MHz memory
• Supports ACPI 2.0 and APM 1.2 System Power Management
• 1.3–1.2 V
• Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
• Sleep Power 5 W
• Deeper Sleep Power = 2.9 W
• * 1.40 GHz – 23 April 2002
• * 1.50 GHz – 23 April 2002
• * 1.60 GHz – 4 March 2002
• * 1.70 GHz – 4 March 2002
• * 1.80 GHz – 23 April 2002
• * 1.90 GHz – 24 June 2002
• * 2.00 GHz – 24 June 2002
• * 2.20 GHz – 16 September 2002
• * 2.40 GHz – 14 January 2003
• * 2.50 GHz – 16 April 2003
• * 2.60 GHz – 11 June 2003

  Pentium 4 EE">P4EE">Pentium 4 EE

• Introduced September 2003
• EE = "Extreme Edition"
• Built from the Xeon's "Gallatin" core, but with 2 MB cache

  Pentium 4E

• Introduced February 2004
• built on 0.09 μm process technology Prescott 1 MB L2 cache
• 533 MHz system bus
• 800 MHz system bus
• 125 million transistors in 1 MB Models
• 169 million transistors in 2 MB Models
• Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
• The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth
• 7500 to 11,000 MIPS
• LGA 775 versions are in the 5xx series and 5x1 series
• The 6xx series has 2 MB L2 cache and Intel 64

  64-bit">64-bit computing">64-bit processors: [IA-64]

• New instruction set, not at all related to x86
• Before the feature was eliminated IA-64 processors supported 32-bit x86 in hardware, but slowly

  Itanium">Itanium (original)">Itanium

• Code name Merced
• Family 7
• Released May 29, 2001
• 733 MHz and 800 MHz
• 2 MB cache
• All recalled and replaced by Itanium 2

  [Itanium 2]

• Family 0x1F
• Released July 2002
• 900 MHz – 1.6 GHz
• McKinley 900 MHz 1.5 MB cache, Model 0x0
• McKinley 1 GHz, 3 MB cache, Model 0x0
• Deerfield 1 GHz, 1.5 MB cache, Model 0x1
• Madison 1.3 GHz, 3 MB cache, Model 0x1
• Madison 1.4 GHz, 4 MB cache, Model 0x1
• Madison 1.5 GHz, 6 MB cache, Model 0x1
• Madison 1.67 GHz, 9 MB cache, Model 0x1
• Hondo 1.4 GHz, 4 MB cache, dual-core MCM, Model 0x1

  64-bit">64-bit computing">64-bit processors: Intel 64 – NetBurst microarchitecture

• Intel Extended Memory 64 Technology
• Mostly compatible with AMD's AMD64 architecture
• Introduced Spring 2004, with the Pentium 4F

  Pentium 4F

• Prescott-2M built on 0.09 μm process technology
• 2.8–3.8 GHz
• Introduced February 20, 2005
• Same features as Prescott with the addition of:
• * 2 MB cache
• * Intel 64-bit
• * Enhanced Intel SpeedStep Technology
• Cedar Mill built on 0.065 μm process technology
• 3.0–3.6 GHz
• Introduced January 16, 2006
• Die shrink of Prescott-2M
• Same features as Prescott-2M
• Family 15 Model 4

  [Pentium D]

• Dual-core microprocessor
• No Hyper-Threading
• 800 MHz front side bus
• LGA 775
• Smithfield – 90 nm process technology
• * Introduced May 26, 2005
• * 2.66–3.2 GHz
• * 230 million transistors
• * 1 MB × 2 L2 cache
• * Cache coherency between cores requires communication over the FSB
• * Performance increase of 60% over similarly clocked Prescott
• * 2.66 GHz Pentium D 805 introduced December 2005
• * Contains 2x Prescott dies in one package
• * Family 15 Model 4
• Presler – 65 nm process technology
• * Introduced January 16, 2006
• * 2.8–3.6 GHz
• * 376 million transistors
• * 2× 2 MB L2 cache
• * Contains 2x Cedar Mill dies in one package
• * Variants
• ** Pentium D 945

  [Pentium Extreme Edition]

• Dual-core microprocessor
• Enabled Hyper-Threading
• 800 MHz front side bus
• Smithfield – 90 nm process technology
• * Variants
• ** Pentium 840 EE – 3.20 GHz
• Presler – 65 nm process technology
• * 2 MB × 2 L2 cache
• * Variants
• ** Pentium 955 EE – 3.46 GHz, 1066 MHz front side bus
• ** Pentium 965 EE – 3.73 GHz, 1066 MHz front side bus
• ** Pentium 969 EE – 3.73 GHz, 1066 MHz front side bus

  [Xeon] (64-bit NetBurst)

• Nocona
• * Introduced 2004
• Irwindale
• * Introduced 2004
• Cranford
• * Introduced April 2005
• * MP version of Nocona
• Potomac
• * Introduced April 2005
• * Cranford with 8 MB of L3 cache
• Paxville DP
• * Introduced October 10, 2005
• * Dual-core version of Irwindale, with 4 MB of L2 cache
• * 2.8 GHz
• * 800 MT/s front side bus
• Paxville MP – 90 nm process
• * Introduced November 1, 2005
• * Dual-core Xeon 7000 series
• * MP-capable version of Paxville DP
• * 2 MB of L2 cache or 4 MB of L2
• * 667 MT/s FSB or 800 MT/s FSB
• Dempsey – 65 nm process
• * Introduced May 23, 2006
• * Dual-core Xeon 5000 series
• * MP version of Presler
• * 667 MT/s or 1066 MT/s FSB
• * 4 MB of L2 cache
• * LGA 771.
• Tulsa – 65 nm process
• * Introduced August 29, 2006
• * Dual-core Xeon 7100-series
• * Improved version of Paxville MP
• * 667 MT/s or 800 MT/s FSB

  64-bit processors: Intel 64 – Core">Core (microarchitecture)">Core microarchitecture

Xeon (64-bit Core microarchitecture)

• Woodcrest – 65 nm process technology
• * Server and Workstation CPU
• * Introduced June 26, 2006
• * Intel VT-x, multiple OS support
• * EIST in 5140, 5148LV, 5150, 5160
• * Execute Disable Bit
• * TXT, enhanced security hardware extensions
• * SSSE3 SIMD instructions
• * iAMT2, remotely manage computers
• * Variants
• ** Xeon 5160 – 3.00 GHz
• ** Xeon 5150 – 2.66 GHz
• ** Xeon 5140 – 2.33 GHz
• ** Xeon 5130 – 2.00 GHz
• ** Xeon 5120 – 1.86 GHz
• ** Xeon 5110 – 1.60 GHz
• ** Xeon 5148LV – 2.33 GHz
• Clovertown – 65 nm process technology
• * Server and Workstation CPU
• * Introduced December 13, 2006
• * Quad-core
• * Intel VT-x, multiple OS support
• * EIST in E5365, L5335
• * Execute Disable Bit
• * TXT, enhanced security hardware extensions
• * SSSE3 SIMD instructions
• * iAMT2, remotely manage computers
• * Variants
• ** Xeon X5355 – 2.66 GHz
• ** Xeon E5345 – 2.33 GHz
• ** Xeon E5335 – 2.00 GHz
• ** Xeon E5320 – 1.86 GHz
• ** Xeon E5310 – 1.60 GHz
• ** Xeon L5320 – 1.86 GHz

  [Intel Core 2]

• Conroe – 65 nm process technology
• * Desktop CPU
• * Two cores on one die
• * Introduced July 27, 2006
• * SSSE3 SIMD instructions
• * 291 million transistors
• * 64 KB of L1 cache per core
• * Intel VT-x, multiple OS support
• * TXT, enhanced security hardware extensions
• * Execute Disable Bit
• * EIST
• * iAMT2, remotely manage computers
• * Intel Management Engine introduced
• * LGA 775
• * Variants
• ** Core 2 Duo E6850 – 3.00 GHz
• ** Core 2 Duo E6800 – 2.93 GHz
• ** Core 2 Duo E6750 – 2.67 GHz
• ** Core 2 Duo E6700 – 2.67 GHz
• ** Core 2 Duo E6600 – 2.40 GHz
• ** Core 2 Duo E6550 – 2.33 GHz
• ** Core 2 Duo E6420 – 2.13 GHz
• ** Core 2 Duo E6400 – 2.13 GHz
• ** Core 2 Duo E6320 – 1.86 GHz Family 6, Model 15, Stepping 6
• ** Core 2 Duo E6300 – 1.86 GHz
• Conroe XE – 65 nm process technology
• * Desktop Extreme Edition CPU
• * Introduced July 27, 2006
• * same features as Conroe
• * LGA 775
• * Variants
• ** Core 2 Extreme X6800 – 2.93 GHz
• Allendale – 65 nm process technology
• * Desktop CPU
• * Two CPUs on one die
• * Introduced January 21, 2007
• * SSSE3 SIMD instructions
• * 167 million transistors
• * TXT, enhanced security hardware extensions
• * Execute Disable Bit
• * EIST
• * iAMT2, remotely manage computers
• * LGA 775
• * Variants
• ** Core 2 Duo E4700 – 2.60 GHz
• ** Core 2 Duo E4600 – 2.40 GHz
• ** Core 2 Duo E4500 – 2.20 GHz
• ** Core 2 Duo E4400 – 2.00 GHz
• ** Core 2 Duo E4300 – 1.80 GHz Family 6, Model 15, Stepping 2
• Merom – 65 nm process technology
• * Mobile CPU
• * Introduced July 27, 2006
• * Family 6, Model 15
• * same features as Conroe
• * Socket M / Socket P
• * Variants
• ** Core 2 Duo T7800 – 2.60 GHz
• ** Core 2 Duo T7700 – 2.40 GHz
• ** Core 2 Duo T7600 – 2.33 GHz
• ** Core 2 Duo T7500 – 2.20 GHz
• ** Core 2 Duo T7400 – 2.16 GHz
• ** Core 2 Duo T7300 – 2.00 GHz
• ** Core 2 Duo T7250 – 2.00 GHz
• ** Core 2 Duo T7200 – 2.00 GHz
• ** Core 2 Duo T7100 – 1.80 GHz
• ** Core 2 Duo T5600 – 1.83 GHz Family 6, Model 15, Stepping 6
• ** Core 2 Duo T5550 – 1.83 GHz
• ** Core 2 Duo T5500 – 1.66 GHz
• ** Core 2 Duo T5470 – 1.60 GHz Family 6, Model 15, Stepping 13
• ** Core 2 Duo T5450 – 1.66 GHz
• ** Core 2 Duo T5300 – 1.73 GHz
• ** Core 2 Duo T5270 – 1.40 GHz
• ** Core 2 Duo T5250 – 1.50 GHz
• ** Core 2 Duo T5200 – 1.60 GHz
• ** Core 2 Duo L7500 – 1.60 GHz
• ** Core 2 Duo L7400 – 1.50 GHz
• ** Core 2 Duo L7300 – 1.40 GHz
• ** Core 2 Duo L7200 – 1.33 GHz
• ** Core 2 Duo U7700 – 1.33 GHz
• ** Core 2 Duo U7600 – 1.20 GHz
• ** Core 2 Duo U7500 – 1.06 GHz
• Kentsfield – 65 nm process technology
• * Two dual-core CPU dies in one package
• * Desktop CPU quad-core
• * Introduced December 13, 2006
• * same features as Conroe but with 4 CPU cores
• * 586 million transistors
• * LGA 775
• * Family 6, Model 15, Stepping 11
• * Variants
• ** Core 2 Extreme QX6850 – 3 GHz
• ** Core 2 Extreme QX6800 – 2.93 GHz
• ** Core 2 Extreme QX6700 – 2.66 GHz
• ** Core 2 Quad Q6700 – 2.66 GHz
• ** Core 2 Quad Q6600 – 2.40 GHz
• Wolfdale – 45 nm process technology
• * Die shrink of Conroe
• * Same features as Conroe with the addition of:
• ** 50% more cache, 6 MB as opposed to 4 MB
• ** Intel Trusted Execution Technology
• ** SSE4 SIMD instructions
• * 410 million transistors
• * Variants
• ** Core 2 Duo E8600 – 3.33 GHz
• ** Core 2 Duo E8500 – 3.16 GHz
• ** Core 2 Duo E8435 – 3.07 GHz
• ** Core 2 Duo E8400 – 3.00 GHz
• ** Core 2 Duo E8335 – 2.93 GHz
• ** Core 2 Duo E8300 – 2.83 GHz
• ** Core 2 Duo E8235 – 2.80 GHz
• ** Core 2 Duo E8200 – 2.66 GHz
• ** Core 2 Duo E8135 – 2.66 GHz
• ** Core 2 Duo E8190 – 2.66 GHz
• Wolfdale-3M – 45 nm process technology
• * Intel Trusted Execution Technology
• * Variants
• ** Core 2 Duo E7600 – 3.06 GHz
• ** Core 2 Duo E7500 – 2.93 GHz
• ** Core 2 Duo E7400 – 2.80 GHz
• ** Core 2 Duo E7300 – 2.66 GHz
• ** Core 2 Duo E7200 – 2.53 GHz
• Yorkfield – 45 nm process technology
• * Quad-core CPU
• * Die shrink of Kentsfield
• * Contains 2x Wolfdale dual-core dies in one package
• * Same features as Wolfdale
• * 820 million transistors
• * Variants
• ** Core 2 Extreme QX9770 – 3.20 GHz
• ** Core 2 Extreme QX9650 – 3.00 GHz
• ** Core 2 Quad Q9705 – 3.16 GHz
• ** Core 2 Quad Q9700 – 3.16 GHz
• ** Core 2 Quad Q9650 – 3 GHz
• ** Core 2 Quad Q9550 – 2.83 GHz
• ** Core 2 Quad Q9550s – 2.83 GHz
• ** Core 2 Quad Q9450 – 2.66 GHz
• ** Core 2 Quad Q9505 – 2.83 GHz
• ** Core 2 Quad Q9505s – 2.83 GHz
• ** Core 2 Quad Q9500 – 2.83 GHz
• ** Core 2 Quad Q9400 – 2.66 GHz
• ** Core 2 Quad Q9400s – 2.66 GHz
• ** Core 2 Quad Q9300 – 2.50 GHz
• ** Core 2 Quad Q8400 – 2.66 GHz
• ** Core 2 Quad Q8400s – 2.66 GHz
• ** Core 2 Quad Q8300 – 2.50 GHz
• ** Core 2 Quad Q8300s – 2.50 GHz
• ** Core 2 Quad Q8200 – 2.33 GHz
• ** Core 2 Quad Q8200s – 2.33 GHz
• ** Core 2 Quad Q7600 – 2.70 GHz
• Intel Core2 Quad Mobile processor family – 45 nm process technology
• * Quad-core CPU
• * Variants
• ** Core 2 Quad Q9100 – 2.26 GHz
• ** Core 2 Quad Q9000 – 2.00 GHz

  [Intel Pentium Dual-Core]

• Allendale – 65 nm process technology
• * Desktop CPU
• * Two cores on one die
• * Introduced January 21, 2007
• * SSSE3 SIMD instructions
• * 167 million transistors
• * TXT, enhanced security hardware extensions
• * Execute Disable Bit
• * EIST
• * Variants
• ** Intel Pentium E2220 – 2.40 GHz
• ** Intel Pentium E2200 – 2.20 GHz
• ** Intel Pentium E2180 – 2.00 GHz
• ** Intel Pentium E2160 – 1.80 GHz
• ** Intel Pentium E2140 – 1.60 GHz
• Wolfdale-3M – 45 nm process technology
• * Intel Pentium E6800 – 3.33 GHz
• * Intel Pentium E6700 – 3.20 GHz
• * Intel Pentium E6600 – 3.06 GHz
• * Intel Pentium E6500 – 2.93 GHz
• * Intel Pentium E6300 – 2.80 GHz
• * Intel Pentium E5800 – 3.20 GHz
• * Intel Pentium E5700 – 3.00 GHz
• * Intel Pentium E5500 – 2.80 GHz
• * Intel Pentium E5400 – 2.70 GHz
• * Intel Pentium E5300 – 2.60 GHz
• * Intel Pentium E5200 – 2.50 GHz
• * Intel Pentium E2210 – 2.20 GHz

  Celeron">Intel Celeron">Celeron (64-bit Core microarchitecture)

• Allendale – 65 nm process technology
• * Variants
• ** Intel Celeron E1600 – 2.40 GHz
• ** Intel Celeron E1500 – 2.20 GHz
• ** Intel Celeron E1400 – 2.00 GHz
• ** Intel Celeron E1300 – 1.80 GHz
• ** Intel Celeron E1200 – 1.60 GHz
• Wolfdale-3M – 45 nm process technology
• * Variants
• ** Intel Celeron E3500 – 2.70 GHz
• ** Intel Celeron E3400 – 2.60 GHz
• ** Intel Celeron E3300 – 2.50 GHz
• ** Intel Celeron E3200 – 2.40 GHz
• Conroe-L – 65 nm process technology
• * Variants
• ** Intel Celeron 450 – 2.20 GHz
• ** Intel Celeron 440 – 2.00 GHz
• ** Intel Celeron 430 – 1.80 GHz
• ** Intel Celeron 420 – 1.60 GHz
• ** Intel Celeron 220 – 1.20 GHz
• Conroe-CL – 65 nm process technology
• * LGA 771 package
• * Variants
• ** Intel Celeron 445 – 1.87 GHz

  [Celeron M] (64-bit Core microarchitecture)

• Merom-L 65 nm process technology
• * 64 KB L1 cache
• * 1 MB L2 cache
• * SSE3 SIMD instructions, 533 MHz/667 MHz front-side bus, execute-disable bit, 64-bit
• * No SpeedStep technology, is not part of the 'Centrino' package
• * Variants
• ** 520 – 1.60 GHz
• ** 530 – 1.73 GHz
• ** 540 – 1.86 GHz
• ** 550 – 2.00 GHz
• ** 560 – 2.13 GHz
• ** 570 – 2.26 GHz

64-bit processors: Intel 64 – Nehalem">Nehalem (microarchitecture)">Nehalem microarchitecture

[Intel Pentium] (Nehalem)

• Clarkdale – 32 nm process technology
• * 2 physical cores/2 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 3 MB L3 cache
• * Introduced January 2010
• * Socket 1156 LGA
• * 2-channel DDR3
• * Integrated HD GPU
• * Variants
• ** G6950 – 2.8 GHz
• ** G6960 – 2.933 GHz

  [Core i3] (1st Generation)

• Clarkdale – 32 nm process technology
• * 2 physical cores/4 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 4 MB L3 cache
• * Introduced on January 7, 2010
• * Socket 1156 LGA
• * 2-channel DDR3
• * Integrated HD GPU
• * Variants
• ** 530 – 2.93 GHz Hyper-Threading
• ** 540 – 3.06 GHz Hyper-Threading
• ** 550 – 3.2 GHz Hyper-Threading
• ** 560 – 3.33 GHz Hyper-Threading

  Core i5">Intel Core i5">Core i5 (1st Generation)

• Lynnfield – 45 nm process technology
• * 4 physical cores/4 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 8 MB L3 cache
• * Introduced September 8, 2009
• * Family 6 Model E
• * Socket 1156 LGA
• * 2-channel DDR3
• * Variants
• ** 750S – 2.40 GHz/3.20 GHz Turbo Boost
• ** 750 – 2.66 GHz/3.20 GHz Turbo Boost
• ** 760 – 2.80 GHz/3.33 GHz Turbo Boost
• Clarkdale – 32 nm process technology
• * 2 physical cores/4 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 4 MB L3 cache
• * Introduced January, 2010
• * Socket 1156 LGA
• * 2-channel DDR3
• * Integrated HD GPU
• * AES Support
• * Variants
• ** 650/655K – 3.2 GHz Hyper-Threading Turbo Boost
• ** 660/661 – 3.33 GHz Hyper-Threading Turbo Boost
• ** 670 – 3.46 GHz Hyper-Threading Turbo Boost
• ** 680 – 3.60 GHz Hyper-Threading Turbo Boost

  Core i7">Intel Core i7">Core i7 (1st Generation)

• Bloomfield – 45 nm process technology
• * 4 physical cores/8 threads
• * 256 KB L2 cache
• * 8 MB L3 cache
• * Front side bus replaced with QuickPath up to 6.4 GT/s
• * Hyper-Threading is again included. This had previously been removed at the introduction of Core line
• * 781 million transistors
• * Intel Turbo Boost Technology
• * TDP 130W
• * Introduced November 17, 2008
• * Socket 1366 LGA
• * 3-channel DDR3
• * Variants
• ** 975 – 3.33 GHz/3.60 GHz Turbo Boost
• ** 965 – 3.20 GHz/3.46 GHz Turbo Boost
• ** 960 – 3.20 GHz/3.46 GHz Turbo Boost
• ** 950 – 3.06 GHz/3.33 GHz Turbo Boost
• ** 940 – 2.93 GHz/3.20 GHz Turbo Boost
• ** 930 – 2.80 GHz/3.06 GHz Turbo Boost
• ** 920 – 2.66 GHz/2.93 GHz Turbo Boost
• Lynnfield – 45 nm process technology
• * 4 physical cores/8 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 8 MB L3 cache
• * No QuickPath, instead compatible with slower DMI interface
• * Hyper-Threading is included
• * Introduced September 8, 2009
• * Socket 1156 LGA
• * 2-channel DDR3
• * Variants
• ** 880 – 3.06 GHz/3.73 GHz Turbo Boost
• ** 870/875K – 2.93 GHz/3.60 GHz Turbo Boost
• ** 870S – 2.67 GHz/3.60 GHz Turbo Boost
• ** 860 – 2.80 GHz/3.46 GHz Turbo Boost
• ** 860S – 2.53 GHz/3.46 GHz Turbo Boost

• Gulftown – 32 nm process technology
• * 6 physical cores
• * 256 KB L2 cache
• * 12 MB L3 cache
• * Front side bus replaced with QuickPath up to 6.4 GT/s
• * Hyper-Threading is included
• * Intel Turbo Boost Technology
• * Socket 1366 LGA
• * TDP 130W
• * Introduced 16 March 2010
• * Variants
• ** 990X Extreme Edition – 3.46 GHz/3.73 GHz Turbo Boost
• ** 980X Extreme Edition – 3.33 GHz/3.60 GHz Turbo Boost
• ** 970 – 3.20 GHz/3.46 GHz Turbo Boost
• Clarksfield – Intel Core i7 Mobile processor family – 45 nm process technology
• * 4 physical cores
• * Hyper-Threading is included
• * Intel Turbo Boost Technology
• * Variants
• ** 940XM Extreme Edition – 2.13 GHz/3.33 GHz Turbo Boost
• ** 920XM Extreme Edition – 2.00 GHz/3.20 GHz Turbo Boost
• ** 840QM – 1.86 GHz/3.20 GHz Turbo Boost
• ** 820QM – 1.73 GHz/3.06 GHz Turbo Boost
• ** 740QM – 1.73 GHz/2.93 GHz Turbo Boost
• ** 720QM – 1.60 GHz/2.80 GHz Turbo Boost

  [Xeon] (Nehalem Microarchitecture)

• Gainestown – 45 nm process technology
• * Same processor dies as Bloomfield
• * 256 KB L2 cache
• * 8 MB L3 cache, 4 MB may be disabled
• * QuickPath up to 6.4 GT/s
• * Hyper-Threading is included in some models
• * 781 million transistors
• * Introduced March 29, 2009
• * Variants
• ** W5590, X5570, X5560, X5550, E5540, E5530, L5530, E5520, L5520, L5518 – 4 cores, 8 MB L3 cache, HT
• ** E5506, L5506, E5504 – 4 cores, 4 MB L3 cache, no HT
• ** L5508, E5502, E5502 – 2 cores, 4 MB L3 cache, no HT

  64-bit processors: Intel 64 – [Sandy Bridge] / Ivy Bridge">Ivy Bridge (microarchitecture)">Ivy Bridge microarchitecture

[Celeron] (Sandy Bridge/Ivy Bridge Microarchitecture)

• Sandy Bridge – 32 nm process technology
• * 2 physical cores/2 threads, 1 physical core/1 thread or 1 physical core/2 threads
• * 2 MB L3 cache, 1 MB or 1.5 MB
• * Introduced 3rd quarter, 2011
• * Socket 1155 LGA
• * 2-channel DDR3-1066
• * 400 series has max TDP of 35 W
• * 500-series variants ending in 'T' have a peak TDP of 35 W, others – 65 W
• * Integrated GPU
• ** All variants have peak GPU turbo frequencies of 1 GHz
• ** Variants in the 400 series have GPUs running at a base frequency of 650 MHz
• ** Variants in the 500 series ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz
• ** All variants have 6 GPU execution units
• * Variants
• ** G440 – 1.6 GHz
• ** G460 – 1.8 GHz
• ** G465 – 1.9 GHz
• ** G470 – 2.0 GHz
• ** G530T – 2.0 GHz
• ** G540T – 2.1 GHz
• ** G550T – 2.2 GHz
• ** G530 – 2.4 GHz
• ** G540 – 2.5 GHz
• ** G550 – 2.6 GHz
• ** G555 – 2.7 GHz

  [Pentium] (Sandy Bridge/Ivy Bridge Microarchitecture)

• Sandy Bridge – 32 nm process technology
• * 2 physical cores/2 threads
• * 3 MB L3 cache
• * 624 million transistors
• * Introduced May, 2011
• * Socket 1155 LGA
• * 2-channel DDR3-1333 or DDR3-1066
• * Variants ending in 'T' have a peak TDP of 35 W, others 65 W
• * Integrated GPU
• ** All variants have peak GPU turbo frequencies of 1.1 GHz
• ** Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz
• ** All variants have 6 GPU execution units
• * Variants
• ** G620T – 2.2 GHz
• ** G630T – 2.3 GHz
• ** G640T – 2.4 GHz
• ** G645T – 2.5 GHz
• ** G860T – 2.6 GHz
• ** G620 – 2.6 GHz
• ** G622 – 2.6 GHz
• ** G630 – 2.7 GHz
• ** G632 – 2.7 GHz
• ** G640 – 2.8 GHz
• ** G840 – 2.8 GHz
• ** G645 – 2.9 GHz
• ** G850 – 2.9 GHz
• ** G860 – 3.0 GHz
• ** G870 – 3.1 GHz
• Ivy Bridge – 22 nm Tri-gate transistor process technology
• * 2 physical cores/2 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 3 MB L3 cache
• * Introduced September, 2012
• * Socket 1155 LGA
• * 2-channel DDR3-1333 for G2000 series
• * 2-channel DDR3-1600 for G2100 series
• * All variants have GPU base frequencies of 650 MHz and peak GPU turbo frequencies of 1.05 GHz
• * Variants ending in 'T' have a peak TDP of 35 W, others – TDP of 55 W
• * Variants
• ** G2020T – 2.5 GHz
• ** G2030T – 2.6 GHz
• ** G2100T – 2.6 GHz
• ** G2120T – 2.7 GHz
• ** G2020 – 2.9 GHz
• ** G2030 – 3.0 GHz
• ** G2120 – 3.1 GHz
• ** G2130 – 3.2 GHz
• ** G2140 – 3.3 GHz

  [Core i3] (2nd and 3rd Generation)

• Sandy Bridge – 32 nm process technology
• * 2 physical cores/4 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 3 MB L3 cache
• * 624 million transistors
• * Introduced January, 2011
• * Socket 1155 LGA
• * 2-channel DDR3-1333
• * Variants ending in 'T' have a peak TDP of 35 W, others 65 W
• * Integrated GPU
• ** All variants have peak GPU turbo frequencies of 1.1 GHz
• ** Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz
• ** Variants ending in '5' have Intel HD Graphics 3000 ; others have Intel HD Graphics 2000
• * Variants
• ** i3-2100T – 2.5 GHz
• ** i3-2120T – 2.6 GHz
• ** i3-2100 – 3.1 GHz
• ** i3-2102 – 3.1 GHz
• ** i3-2105 – 3.1 GHz
• ** i3-2120 – 3.3 GHz
• ** i3-2125 – 3.3 GHz
• ** i3-2130 – 3.4 GHz
• Ivy Bridge – 22 nm Tri-gate transistor process technology
• * 2 physical cores/4 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 3 MB L3 cache
• * Introduced September, 2012
• * Socket 1155 LGA
• * 2-channel DDR3-1600
• * Variants ending in '5' have Intel HD Graphics 4000; others have Intel HD Graphics 2500
• * All variants have GPU base frequencies of 650 MHz and peak GPU turbo frequencies of 1.05 GHz
• * TDP 55 W
• * Variants
• ** i3-3220T – 2.8 GHz
• ** i3-3240T – 2.9 GHz
• ** i3-3210 – 3.2 GHz
• ** i3-3220 – 3.3 GHz
• ** i3-3225 – 3.3 GHz
• ** i3-3240 – 3.4 GHz

  Core i5">Intel Core i5">Core i5 (2nd and 3rd Generation)

• Sandy Bridge – 32 nm process technology
• * 4 physical cores/4 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 6 MB L3 cache
• * 995 million transistors
• * Introduced January, 2011
• * Socket 1155 LGA
• * 2-channel DDR3-1333
• * Variants ending in 'S' have a peak TDP of 65 W, others – 95 W except where noted
• * Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
• * Integrated GPU
• ** i5-2500T has a peak GPU turbo frequency of 1.25 GHz, others 1.1 GHz
• ** Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz
• ** Variants ending in '5' or 'K' have Intel HD Graphics 3000, except i5-2550K which has no GPU; others have Intel HD Graphics 2000
• ** Variants ending in 'P' and the i5-2550K have no GPU
• * Variants
• ** i5-2390T – 2.7 GHz/3.5 GHz Turbo Boost
• ** i5-2500T – 2.3 GHz/3.3 GHz Turbo Boost
• ** i5-2400S – 2.5 GHz/3.3 GHz Turbo Boost
• ** i5-2405S – 2.5 GHz/3.3 GHz Turbo Boost
• ** i5-2500S – 2.7 GHz/3.7 GHz Turbo Boost
• ** i5-2300 – 2.8 GHz/3.1 GHz Turbo Boost
• ** i5-2310 – 2.9 GHz/3.2 GHz Turbo Boost
• ** i5-2320 – 3.0 GHz/3.3 GHz Turbo Boost
• ** i5-2380P – 3.1 GHz/3.4 GHz Turbo Boost
• ** i5-2400 – 3.1 GHz/3.4 GHz Turbo Boost
• ** i5-2450P – 3.2 GHz/3.5 GHz Turbo Boost
• ** i5-2500 – 3.3 GHz/3.7 GHz Turbo Boost
• ** i5-2500K – 3.3 GHz/3.7 GHz Turbo Boost
• ** i5-2550K – 3.4 GHz/3.8 GHz Turbo Boost
• Ivy Bridge – 22 nm Tri-gate transistor process technology
• * 4 physical cores/4 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 6 MB L3 cache
• * Introduced April, 2012
• * Socket 1155 LGA
• * 2-channel DDR3-1600
• * Variants ending in 'S' have a peak TDP of 65 W, Variants ending in 'T' have a peak TDP of 35 or 45 W, others – 77 W except where noted
• * Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
• * Variants ending in 'P' have no integrated GPU; others have Intel HD Graphics 2500 or Intel HD Graphics 4000
• * Variants
• ** i5-3470T – 2.9 GHz/3.6 GHz max Turbo Boost
• ** i5-3570T – 2.3 GHz/3.3 GHz max Turbo Boost
• ** i5-3330S – 2.7 GHz/3.2 GHz max Turbo Boost
• ** i5-3450S – 2.8 GHz/3.5 GHz max Turbo Boost
• ** i5-3470S – 2.9 GHz/3.6 GHz max Turbo Boost
• ** i5-3475S – 2.9 GHz/3.6 GHz max Turbo Boost
• ** i5-3550S – 3.0 GHz/3.7 GHz max Turbo Boost
• ** i5-3570S – 3.1 GHz/3.8 GHz max Turbo Boost
• ** i5-3330 – 3.0 GHz/3.2 GHz max Turbo Boost
• ** i5-3350P – 3.1 GHz/3.3 GHz max Turbo Boost
• ** i5-3450 – 3.1 GHz/3.5 GHz max Turbo Boost
• ** i5-3470 – 3.2 GHz/3.6 GHz max Turbo Boost
• ** i5-3550 – 3.3 GHz/3.7 GHz max Turbo Boost
• ** i5-3570 – 3.4 GHz/3.8 GHz max Turbo Boost
• ** i5-3570K – 3.4 GHz/3.8 GHz max Turbo Boost

  Core i7">Intel Core i7">Core i7 (2nd and 3rd Generation)

• Sandy Bridge – 32 nm process technology
• * 4 physical cores/8 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 8 MB L3 cache
• * 995 million transistors
• * Introduced January, 2011
• * Socket 1155 LGA
• * 2-channel DDR3-1333
• * Variants ending in 'S' have a peak TDP of 65 W, others – 95 W
• * Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
• * Integrated GPU
• ** All variants have base GPU frequencies of 850 MHz and peak GPU turbo frequencies of 1.35 GHz
• ** Variants ending in 'K' have Intel HD Graphics 3000 ; others have Intel HD Graphics 2000
• * Variants
• ** i7-2600S – 2.8 GHz/3.8 GHz Turbo Boost
• ** i7-2600 – 3.4 GHz/3.8 GHz Turbo Boost
• ** i7-2600K – 3.4 GHz/3.8 GHz Turbo Boost
• ** i7-2700K – 3.5 GHz/3.9 GHz Turbo Boost
• Sandy Bridge-E – 32 nm process technology
• * Up to 6 physical cores/12 threads depending on model number
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * Up to 20 MB L3 cache depending on model number
• * 2.27 billion transistors
• * Introduced November, 2011
• * Socket 2011 LGA
• * 4-channel DDR3-1600
• * All variants have a peak TDP of 130 W
• * No integrated GPU
• * Variants
• ** i7-3820 – 3.6 GHz/3.8 GHz Turbo Boost, 4 cores, 10 MB L3 cache
• ** i7-3930K – 3.2 GHz/3.8 GHz Turbo Boost, 6 cores, 12 MB L3 cache
• ** i7-3960X – 3.3 GHz/3.9 GHz Turbo Boost, 6 cores, 15 MB L3 cache
• ** i7-3970X – 3.5 GHz/4.0 GHz Turbo Boost, 6 cores, 15 MB L3 cache
• Ivy Bridge – 22 nm Tri-gate transistor process technology
• * 4 physical cores/8 threads
• * 32+32 KB L1 cache
• * 256 KB L2 cache
• * 8 MB L3 cache
• * Introduced April, 2012
• * Socket 1155 LGA
• * 2-channel DDR3-1600
• * Variants ending in 'S' have a peak TDP of 65 W, variants ending in 'T' have a peak TDP of 45 W, others – 77 W
• * Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
• * Integrated GPU Intel HD Graphics 4000
• * Variants
• ** i7-3770T – 2.5 GHz/3.7 GHz Turbo Boost
• ** i7-3770S – 3.1 GHz/3.9 GHz Turbo Boost
• ** i7-3770 – 3.4 GHz/3.9 GHz Turbo Boost
• ** i7-3770K – 3.5 GHz/3.9 GHz Turbo Boost

  64-bit processors: Intel 64 – Haswell">Haswell (microarchitecture)">Haswell microarchitecture

[Core i3] (4th Generation)

• Haswell – 22nm process technology

  64-bit processors: Intel 64 – Broadwell">Broadwell (microarchitecture)">Broadwell microarchitecture

[Core i3] (5th Generation)

• Broadwell – 14nm process technology

  [Core i5] (5th Generation)

• Broadwell – 14nm process technology
• * 4 physical cores/4 threads
• * 4 MB L3 cache
• * Introduced Q2'15
• * Socket 1150 LGA
• * 2-channel DDR3L-1333/1600
• * Integrated GPU
• * Variants
• ** i5-5575R – 2.80 GHz/3.30 GHz Turbo Boost
• ** i5-5675C – 3.10 GHz/3.60 GHz Turbo Boost
• ** i5-5675R – 3.10 GHz/3.60 GHz Turbo Boost

  [Core i7] (5th Generation, Including Core-X Series)

• Broadwell – 14nm process technology
• * 4 physical cores/8 threads
• * 6 MB L3 cache
• * Introduced Q2'15
• * Socket 1150 LGA
• * 2-channel DDR3L-1333/1600
• * Integrated GPU
• * Variants
• ** i7-5775C – 3.30 GHz/3.70 GHz Turbo Boost
• ** i7-5775R – 3.30 GHz/3.80 GHz Turbo Boost
• Broadwell-E – 14nm process technology
• * 6–10 physical cores/12–20 threads
• * 15–25 MB L3 cache
• * Introduced Q2'16
• * Socket 2011-v3 LGA
• * 4-channel DDR4-2133/2400
• * No Integrated GPU
• * Variants
• ** i7-6800K – 3.40 GHz/3.60 GHz Turbo Boost/3.80 GHz Turbo Boost Max Technology 3.0 Frequency 15 MB L3 cache
• ** i7-6850K – 3.60 GHz/3.80 GHz Turbo Boost/4.00 GHz Turbo Boost Max Technology 3.0 Frequency 15 MB L3 cache
• ** i7-6900K – 3.20 GHz/3.70 GHz Turbo Boost/4.00 GHz Turbo Boost Max Technology 3.0 Frequency 20 MB L3 cache
• ** i7-6950X – 3.00 GHz/3.50 GHz Turbo Boost/4.00 GHz Turbo Boost Max Technology 3.0 Frequency 25 MB L3 cache

  Other Broadwell CPUs

• Server and workstation CPUs
• *single-CPU: Pentium D15nn, Xeon D-15nn, Xeon E3-12nn v4, Xeon E5-16nn v4
• *dual-CPU: Xeon E5-26nn v4
• *quad-CPU: Xeon E5-46nn v4, Xeon E7-48nn v4
• *octo-CPU: Xeon E7-88nn v4
• Embedded CPUs
• *Core i7-57nnEQ, Core i7-58nnEQ
• Mobile CPUs
• *Celeron 32nnU, Celeron 37nnU
• *Pentium 38nnU
• *Core M-5Ynn
• *Core i3-50nnU
• *Core i5-5nnnU
• *Core i7-55nnU, Core i7-56nnU, Core i7-57nnHQ, Core i7-59nnHQ

64-bit">64-bit computing">64-bit processors: Intel 64 – Skylake">Skylake (microarchitecture)">Skylake microarchitecture

[Core i3] (6th Generation)

• Skylake – 14 nm process technology
• * 2 physical cores/4 threads
• * 3–4 MB L3 cache
• * Introduced Q3'15
• * Socket 1151 LGA
• * 2-channel DDR3L-1333/1600, DDR4-1866/2133
• * Integrated GPU Intel HD Graphics 530
• * Variants
• ** i3-6098P – 3.60 GHz
• ** i3-6100T – 3.20 GHz
• ** i3-6100 – 3.70 GHz
• ** i3-6300T – 3.30 GHz
• ** i3-6300 – 3.80 GHz
• ** i3-6320 – 3.90 GHz

  [Core i5] (6th Generation)

• Skylake – 14nm process technology
• * 4 physical cores/4 threads
• * 6 MB L3 cache
• * Introduced Q3'15
• * Socket 1151 LGA
• * 2-channel DDR3L-1333/1600, DDR4-1866/2133
• * Integrated GPU Intel HD Graphics 530
• * Variants
• ** i5-6400T – 2.20 GHz/2.80 GHz Turbo Boost
• ** i5-6400 – 2.70 GHz/3.30 GHz Turbo Boost
• ** i5-6500T – 2.50 GHz/3.10 GHz Turbo Boost
• ** i5-6500 – 3.20 GHz/3.60 GHz Turbo Boost
• ** i5-6600T – 2.70 GHz/3.50 GHz Turbo Boost
• ** i5-6600 – 3.30 GHz/3.90 GHz Turbo Boost
• ** i5-6600K – 3.50 GHz/3.90 GHz Turbo Boost

  [Core i7] (6th Generation)

• Skylake – 14nm process technology
• * 4 physical cores/8 threads
• * 8 MB L3 cache
• * Introduced Q3'15
• * Socket 1151 LGA
• * 2-channel DDR3L-1333/1600, DDR4-1866/2133
• * Integrated GPU Intel HD Graphics 530
• * Variants
• ** i7-6700T – 2.80 GHz/3.60 GHz Turbo Boost
• ** i7-6700 – 3.40 GHz/4.00 GHz Turbo Boost
• ** i7-6700K – 4.00 GHz/4.20 GHz Turbo Boost

  Other Skylake Processors

64-bit processors: Intel 64 – Kaby Lake">Kaby Lake (microarchitecture)">Kaby Lake microarchitecture

64-bit processors: Intel 64 – [Coffee Lake] microarchitecture

64-bit processors: Intel 64 – Cannon Lake">Cannon Lake (microarchitecture)">Cannon Lake microarchitecture

64-bit processors: Intel 64 – Ice Lake">Ice Lake (microarchitecture)">Ice Lake microarchitecture

64-bit processors: Intel 64 – [Comet Lake] microarchitecture

[Intel Tera-Scale]

• 2007: Teraflops Research Chip, an 80 cores processor prototype.
• 2009: Single-chip Cloud Computer, a research microprocessor containing the most Intel Architecture cores ever integrated on a silicon CPU chip – 48 cores.

  Intel 805xx product codes

Intel 806xx product codes

Intel 807xx Product Codes