List of Xilinx FPGAs This page contains general information about field-programmable gate array devices from Xilinx , based on official specifications.Terminology The fields in the table listed below describe the following: Model – The marketing name for the device, assigned by Xilinx. Launch – Date when the product was announced. Sub-models – Some FPGA models have multiple sub-models. Flip-Flops – The number of flip-flops embedded within the FPGA fabric. LUTs – The number of lookup tables embedded within the FPGA fabric. DSP Slices – The number of digital signal processor slices embedded within the FPGA fabric. Peak DSP Performance – The maximum number of multiply-accumulate operations per second that can be performed by the digital signal processors that are embedded within the FPGA fabric. This is a theoretical best-case number. PCIe – Bus by which the device is attached to an external system. Max Distributed RAM – Random Access Memory within the LUTs. Total Block RAM – On-chip RAM that is not integrated within the LUTs. UltraRAM – An additional block of RAM that was introduced with the Zynq UltraScale+ FPGA line. UltraRAM can be powered down for extended periods of time.FPGAs with onboard CPUs ">Central processing unit">CPUs Zynq 7000-series Model Launch Flip-Flops LUTs DSP Slices Peak DSP Performance PCIe Z-7010 2011 35.2 17.6 80 100 - Z-7015 92.4 46.2 160 200 Gen2 x4 Z-7020 2011 106.4 53.2 220 276 - Z-7030 2011 157.2 78.6 400 593 Gen2 x4 Z-7035 343.8 171.9 900 1334 Gen2 x8 Z-7045 437.2 218.6 900 1334 Gen2 x8 Z-7100 2013 554.8 277.4 2020 2622 Gen2 x8
Zynq UltraScale+ Xilinx announced the Zynq UltraScale+ line in 2015 All models are manufactured using a 16 nm fabrication process Model Launch Sub-models Flip-Flops LUTs DSP Slices PCIe Max Distributed RAM Total Block RAM UltraRAM ZU2 CG , EG94 47 240 Gen2 x4 1.2 5.3 - ZU3 CG, EG 141 71 360 Gen2 x4 1.8 7.6 - ZU4 CG, EG, EV 176 88 728 Gen2 x4 2.6 4.5 13.5 ZU5 CG, EG, EV 234 117 1248 Gen2 x4 3.5 5.1 18 ZU6 CG, EG 429 215 1973 Gen2 x4 6.9 25.1 - ZU7 CG, EG, EV 461 230 1728 Gen2 x4 6.2 11 27 ZU9 CG, EG 548 274 2520 Gen2 x4 8.8 32.1 - ZU11 EG 597 299 2928 Gen2 x4 9.1 21.1 22.5 ZU15 EG 682 341 3528 Gen2 x4 11.3 26.2 31.5 ZU17 EG 847 423 1590 Gen2 x4 8 28 28.7 ZU19 EG 1045 523 1968 Gen2 x4 9.8 34.6 36
Sub-models of Zynq UltraScale+ Each model of Zynq UltraScale+ is available in up to 3 sub-models: CG, EG, and EV. The main differences among these sub-models are in the CPU and GPU configurations.CG EG EV APU 2x Arm A53 4x Arm A53 4x Arm A53 RPU 2x Arm R5 2x Arm R5 2x Arm R5 GPU - Arm Mali-400MP2 Arm Mali-400MP2 VCU - - H.264/H.265
Versal In 2018, Xilinx announced a product line called Versal. Versal chips will contain CPU, GPU, DSP, and FPGA components. Versal will be fabricated using 7nm process technology. Xilinx has stated that Versal products will be available in the second half of 2019.FPGAs without onboard CPUs XC-series Spartan Virtex ">Virtex (FPGA)">VirtexArtix Kintex
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