M·CORE
M·CORE is a low-power, RISC-based microcontroller architecture developed by Motorola, intended for use in embedded systems. Introduced in late 1997, the architecture combines a 32-bit internal data path with 16-bit instructions, and includes a four-stage instruction pipeline. Initial implementations used a 0.36 micrometre process and ran at 50 MHz.
M·CORE processors employ a von Neumann architecture with shared program and data bus—executing instructions from within data memory is possible. Motorola engineers designed M·CORE to have low power consumption and high code density.
The CK610 CPU developed by C-SKY is fully compatible with M·CORE and has Linux compatibility.
