MCST-R1000

MCST R1000 Highlights

• implements the SPARC V9 instruction set architecture
• quad-core
• core specifications:
• *in-order, dual-issue superscalar
• *7-stage integer pipeline
• *9-stage floating-point pipeline
• *VIS extensions 1 and 2
• *Multiply–accumulate unit
• *16 KB L1 instruction cache
• *32 KB L1 data cache
• *size 7.6 mm²
• shared 2MB L2 cache
• integrated memory controller
• integrated ccNUMA controller
• 1 GHz clock rate
• 90 nm process
• die size 128 mm²
• ~150 million transistors
• power consumption 15W