Open collector


An open collector is a common type of output found on many integrated circuits, which behaves like a switch that is either connected to ground or disconnected. Instead of outputting a signal of a specific voltage or current, the output signal is applied to the base of an internal NPN transistor whose collector is externalized on a pin of the IC. The emitter of the transistor is connected internally to the ground pin. If the output device is a MOSFET the output is called open drain and it functions in a similar way. For example, the I²C bus is based on this concept.

Function

In the picture, the transistor base is labeled "IC output". This is a signal from the internal IC logic to the transistor. This signal controls the transistor switching. The external output is the transistor collector; the transistor forms an interface between the internal IC logic and parts external to the IC.
On schematic component symbols, the open output is indicated with these symbols:
The output forms either an open circuit or a connection to ground. The output usually consists of an external pull-up resistor, which raises the output voltage when the transistor is turned off. When the transistor connected to this resistor is turned on, the output is forced to nearly 0 volts. Open-collector outputs can be useful for analog weighting, summing, limiting, etc., but such applications are not discussed here.
A three-state logic device is unlike an open collector device, because it comprises transistors to source and sink current in both logic states, as well as a control to turn off both transistors and isolate the output.

Applications of open-collector devices

Because the pull-up resistor is external and does not need to be connected to the chip supply voltage, a lower or higher voltage than the chip supply voltage can be used instead. Open collector circuits are therefore sometimes used to interface different families of devices that have different operating voltage levels. The open-collector transistor can be rated to withstand a higher voltage than the chip supply voltage. This technique is commonly used by logic circuits operating at 5 V or lower to drive devices such as motors, 12 V relays, 50 V vacuum fluorescent displays, or Nixie tubes requiring more than 100 V.
Another advantage is that more than one open-collector output can be connected to a single line. If all outputs attached to the line are in the high-impedance state, the pull-up resistor will hold the wire in a high voltage state. If one or more device outputs are in the logic 0 state, they will sink current and pull the line voltage toward ground. This wired logic connection has several uses. Open-collector devices are commonly used to connect multiple devices to one interrupt request signal or a shared bus such as I²C. This enables one device to drive the bus without interference from the other inactive devices. If open-collector devices were not used, then the outputs of the inactive devices would attempt to hold the bus voltage high, resulting in unpredictable output.
By tying the output of several open collectors together, the common line becomes a "wired AND" or "wired OR" gate. A "wired AND" behaves like the boolean AND of the two gates in that it will be logic 1 whenever are in the high impedance state, and 0 otherwise. A "wired OR" behaves like the Boolean OR for negative-true logic, where the output is LOW if any of its inputs are low.
SCSI-1 devices use open collector for electrical signaling. SCSI-2 and SCSI-3 may use EIA-485.
One problem with open-collector devices is power consumption, since the pullup resistor dissipates power whenever the output is pulled low, and the higher the desired operating speed, the lower the resistor value needs to be, resulting in increased consumption. Even in the 'off' state, they often have a few nanoamperes of leakage current.

MOSFET

The analogous connection used with MOS transistors is an open-drain connection. Open-drain outputs can be useful for analog weighting, summing, and limiting as well as digital logic. An open drain terminal is connected to ground when a high voltage is applied to the gate, yet presents a high impedance when a low voltage is applied to the gate. This high impedance state occurs because the terminal is at an undefined voltage thus such a device requires an external pull-up resistor connected to the positive voltage rail in order to provide a logic 1 as output.
Microelectronic devices using open drain signals may provide a weak internal pull-up resistor to connect the terminal in question to the positive power supply of the device. Such weak pullups, often on the order of 100 kΩ, reduce power usage by keeping input signals from floating and may avoid the need for an external pull-up component. External pullups are stronger to reduce signal rise times or to minimize noise. Internal pullups can usually be disabled if they are not wanted.

POD Pseudo open drain

The pseudo open drain drivers have a strong pull-down strength but a weaker pullup strength. A pure open-drain driver, by comparison, has no pullup strength except for leakage current: all the pull-up action is on the external termination resistor. This is why the term "pseudo" has to be used here: there is some pull-up on the driver side when output is at high state, the remaining pull-up strength is provided by parallel-terminating the receiver at the far end to the HIGH voltage, often using a switchable, on-die terminator instead of a separate resistor. The purpose of all this is to reduce the overall power demand compared to using both strong pullup and strong pull-down, as in drivers such as HSTL. DDR4 memory uses POD12 drivers but with the same driver strength for pull-down and pull-up. The term POD in DDR4 referring only for termination type that is only parallel pull-up without the pull-down termination at the far end. The reference point for the input is not half-supply as was in DDR3 and may be higher.
JEDEC standardized the POD15, the POD125, the POD135 and the POD12 for 1.5V, 1.35V and 1.2V interface supply voltages. A comparison of both DDR3 and DDR4 termination schemes in terms of skew, eye aperture and power consumption was published in late 2011.