Power–delay product
In digital electronics, the power–delay product is a figure of merit correlated with the energy efficiency of a logic gate or logic family. Also known as switching energy, it is the product of power consumption P times the input–output delay or duration of the switching event D. It has the dimension of energy and measures the energy consumed per switching event.
In a CMOS circuit the switching energy and thus the PDP for a 0-to-1-to-0 computation cycle is CL·VDD2. Therefore, lowering the supply voltage VDD lowers the PDP.
Energy-efficient circuits with a low PDP may also be performing very slowly, thus energy–delay product, the product of E and D, is sometimes a preferable metric.
In CMOS circuits the delay is inversely proportional to the supply voltage VDD and hence EDP is proportional to VDD. Consequently, lowering VDD also benefits EDP.
