Power integrity or PI is an analysis to check whether the desired voltage and current are met from source to destination. Today, power integrity plays a major role in the success and failure of new electronic products. There are several coupled aspects of PI: on the chip, in the chip package, on the circuit board, and in the system. Four main issues must be resolved to ensure power integrity at the printed circuit board level:
Keep the voltage ripple at the chips pads lower than the specification
Control electromagnetic interference and maintain electromagnetic compatibility: the power distribution network is generally the largest set of conductors on the circuit board and therefore the largest antenna for emission and reception of noise.
Maintaining a proper DC Voltage level at the load at high currents. A modern processor or field-programmable gate array can pull 1-100 Amps at sub-1V VDD levels with AC and DC margins in the tens of millivolts. Very little DC voltage drop can thus be tolerated on the power distribution network.
The current path from the power supply through the PCB and IC package to the die is called the power distribution network. Its role is to transfer the power to the consumers with little DC voltage drop, and to allow little ripple induced by dynamic current at the consumer. The DC drop occurs if there is too much resistance in the plane or power traces leading from the VRM to the consumer. This can be countered by raising the voltage on the VRM, or extending the "sense" point of the VRM to the consumer. Dynamic current occur when the consumer switches its transistors, typically triggered by a clock. This dynamic current can be considerably larger than the static current of the consumer. This fast current consumption can pull the voltage of the rail down, creating a voltage ripple. This change in current happens much faster than the VRM can react. The switching current must therefore be handled by decoupling capacitors. The noise or voltage ripple must be handled differently depending on the frequency of operation. The highest frequencies must be handled on-die. This noise is decoupled by parasitic coupling in on the die, and capacitive coupling between metal layers. Frequencies above 50-100 MHz must be handled on the package, this is done by on package capacitors. Frequencies below 100 MHz are handled on the PCB by plane capacitance and using decoupling capacitors. Capacitors work on different frequencies depending on their type, capacitance and physical size. It is therefore necessary to utilize multiple capacitors of different sizes to ensure a low PDN impedance across the frequency range. The physical size of the capacitors affect its parasitic inductance. The parasitic inductance creates impedance spikes at certain frequencies. Smaller capacitors are therefore better. The placement of the capacitors is of varying importance depending on its frequency of operation. The smallest value capacitors should be as close as possible to the consumer to minimize the AC current loop area. Larger capacitors in the micro Farad range can be placed more or less anywhere.
Target impedance
The target impedance is the impedance at which the ripple created by the dynamic current of the specific consumer is within the specified range. The target impedance is given by the following equation In addition to the target impedance, it is important to know which frequencies it applies, and at which frequency the consumer package is responsible. One usually use some form of simulation when designing the PDN to ensure that the PDN meets the target impedance. This can be done by SPICE simulation, chip vendor tools, capacitor venor tools, or by tools embedded in the EDA software.
