Power management is a feature of some electrical appliances, especially copiers, computers, CPUs, GPUs and computer peripherals such as monitors and printers, that turns off the power or switches the system to a low-power state when inactive. In computing this is known as PC power management and is built around a standard called ACPI. This supersedes APM. All recent computers have ACPI support.
Lower power consumption also means lower heat dissipation, which increases system stability, and less energy use, which saves money and reduces the impact on the environment.
Processor level techniques
The power management for microprocessors can be done over the whole processor, or in specific components, such as cache memory and main memory. With dynamic voltage scaling and dynamic frequency scaling, the CPU core voltage, clock rate, or both, can be altered to decrease power consumption at the price of potentially lower performance. This is sometimes done in real time to optimize the power-performance tradeoff. Examples:
When a computer system hibernates it saves the contents of the RAM to disk and powers down the machine. On startup it reloads the data. This allows the system to be completely powered off while in hibernate mode. This requires a file the size of the installed RAM to be placed on the hard disk, potentially using up space even when not in hibernate mode. Hibernate mode is enabled by default in some versions of Windows and can be disabled in order to recover this disk space.
In GPUs
Graphics processing unit are used together with a CPU to accelerate computing in variety of domains revolving around scientific, analytics, engineering, consumer and enterprise applications. All of this do come with some drawbacks, the high computing capability of GPUs comes at the cost of high power dissipation. Much research has been done over the power dissipation issue of GPUs and many techniques have been proposed to address this issue.Dynamic voltage scaling/dynamic frequency scaling and clock gating are two commonly used techniques for reducing dynamic power in GPUs.
DVFS techniques
Experiments show that conventional processor DVFS policy can achieve power reduction of embedded GPUs with reasonable performance degradation. New directions for designing effective DVFS schedulers for heterogeneous systems are also being explored. A heterogeneous CPU-GPU architecture, GreenGPU is presented which employs DVFS in a synchronized way, both for GPU and CPU. GreenGPU is implemented using the CUDA framework on a real physical testbed with Nvidia GeForce GPUs and AMD Phenom II CPUs. Experimentally it is shown that the GreenGPU achieves 21.04% average energy saving and outperforms several well-designed baselines. For the mainstream GPUs which are extensively used in all kinds of commercial and personal applications several DVFS techniques exist and are built into the GPUs alone, AMD PowerTune and AMD ZeroCore Power are the two dynamic frequency scaling technologies for AMD graphic cards. Practical tests showed that reclocking a Geforce GTX 480 can achieve a 28% lower power consumption while only decreasing performance by 1% for a given task.
Much research has been done on the dynamic power reduction with the use of DVFS techniques. However, as technology continues to shrink, leakage power will become a dominant factor. Power gating is a commonly used circuit technique to remove leakage by turning off the supply voltage of unused circuits. Power gating incurs energy overhead; therefore, unused circuits need to remain idle long enough to compensate this overheads. A novel micro-architectural technique for run-time power-gating caches of GPUs saves leakage energy. Based on experiments on 16 different GPU workloads, the average energy savings achieved by the proposed technique is 54%. Shaders are the most power hungry component of a GPU, a predictive shader shut downpower gating technique achieves up to 46% leakage reduction on shader processors. The Predictive Shader Shutdown technique exploits workload variation across frames to eliminate leakage in shader clusters. Another technique called Deferred Geometry Pipeline seeks to minimize leakage in fixed-function geometry units by utilizing an imbalance between geometry and fragment computation across batches which removes up to 57% of the leakage in the fixed-function geometry units. A simple time-out power gating method can be applied to non-shader execution units which eliminates 83.3% of the leakage in non-shader execution units on average. All the three techniques stated above incur negligible performance degradation, less than 1%.
