RDNA (microarchitecture)


RDNA is the codename for a GPU microarchitecture and accompanying instruction set developed by AMD. It is the successor to their Graphics Core Next microarchitecture/instruction set. The first product lineup featuring RDNA was the Radeon RX 5000 series of video cards, launched on July 7, 2019. The architecture is also planned to be used in mobile products and the upcoming next generation of game consoles by Sony and Microsoft, both of which will use RDNA2-based graphics.
It is likely to be RISC SIMD microarchitecture. It is manufactured and fabricated with TSMC's 7 nm FinFET graphics chips used in the Navi series of AMD Radeon graphics cards.

Architecture

The architecture features a new processor design, although the first details released at AMD's Computex keynote hints at aspects from the previous a Graphics Core Next architecture being present. It will feature multi-level cache hierarchy and an improved rendering pipeline, with support for GDDR6 memory. A completely redesigned architecture is planned as a successor.
Starting with the architecture itself, one of the biggest changes for RDNA is the width of a wavefront, the fundamental group of work. GCN in all of its iterations was 64 threads wide, meaning 64 threads were bundled together into a single wavefront for execution. RDNA drops this to a native 32 threads wide. At the same time, AMD has expanded the width of their SIMDs from 16 slots to 32, meaning the size of a wavefront now matches the SIMD size.
RDNA also introduces working primitive shaders. While the feature was present in the hardware of the Vega architecture, it was difficult to get a real-world performance boost from and thus AMD never enabled it. Primitive shaders in RDNA are compiler-controlled.
The display controller in RDNA has been updated to support Display Stream Compression 1.2a, allowing output in 4k@240 Hz, HDR 4K@120 Hz, and HDR 8K@60 Hz.

Instruction set

AMD's GPUOpen website hosts a PDF document aiming to describe the environment, the organization and the program state of AMD “RDNA” Generation devices. It details the instruction set and the microcode formats native to this family of processors that are accessible to programmers and compilers.
The RDNA instruction set is owned by AMD.

Differences between GCN and RDNA 1

There are architectural changes which affect how code is scheduled:
  1. Single cycle instruction issue:
  2. *GCN issued one instruction per wave once every 4 cycles.
  3. *RDNA issues instructions every cycle.
  4. Wave32:
  5. *GCN used a wavefront size of 64 threads.
  6. *RDNA supports both wavefront sizes of 32 and 64 threads.
  7. Workgroup Processors:
  8. *GCN grouped the shader hardware into "compute units" which contained scalar ALUs and vector ALUs, LDS and memory access. One CU contains 4 SIMD16s which share one path to memory.
  9. *RDNA introduced the "workgroup processor". The WGP replaces the compute unit as the basic unit of shader computation hardware/computing. One WGP encompasses 2 CUs. This allows significantly more compute power and memory bandwidth to be directed at a single workgroup. In RDNA 1 CU is one half of a WGP.

    RDNA 2

RDNA 2 is the successor to the RDNA 1 microarchitecture and is planned to be released in 2020. According to statements from AMD, RDNA 2 will be a "refresh" of the RDNA 1 architecture.
More information about RDNA 2 was made public on AMD's Financial Analyst Day on March 5th, 2020. AMD claims it will provide a 50% performance-per-watt improvement over RDNA 1 and, although no exact figures were provided yet, increases in clock speed and instructions-per-clock. Additional features confirmed by AMD include real-time, hardware accelerated ray tracing and variable rate shading. RDNA 2 will be used in next-generation gaming consoles and PC graphics cards code-named "Navi 2X".

Usage in ninth-generation gaming consoles

RDNA 2 has been confirmed as the graphics microarchitecture that will be used in the upcoming ninth-generation gaming consoles, with proprietary tweaks and different GPU configurations in each systems' implementation.