Semiconductor intellectual property core


In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone. The term is derived from the licensing of the patent and/or source code copyright that exist in the design. IP cores can be used as building blocks within application-specific integrated circuit designs or field-programmable gate array logic designs.

History

The licensing and use of IP cores in chip design came into common practice in the 1990s. There were many licensors and also many foundries competing on the market. Today, the most widely licensed IP cores are from Arm Holdings, Synopsys Inc., Imagination Technologies and Cadence Design Systems.

Types of IP cores

The IP core serves for chip design the same purpose a library serves for computer programming or a discrete integrated circuit component does for printed circuit board design. In each case, it is a reusable component of design logic with a defined interface and behavior that has been verified by its vendor and is integrated into a larger software or hardware design.

Soft cores

IP cores are typically offered as synthesizable RTL. Synthesizable cores are delivered in a hardware description language such as Verilog or VHSIC hardware description language. These are analogous to low level languages such as C in the field of computer programming. IP cores delivered to chip designers as RTL permit chip designers to modify designs at the functional level, though many IP vendors offer no warranty or support for modified designs.
IP cores are also sometimes offered as generic gate-level netlists. The netlist is a boolean-algebra representation of the IP's logical function implemented as generic gates or process specific standard cells. An IP core implemented as generic gates is portable to any process technology. A gate-level netlist is analogous to an assembly code listing in the field of computer programming. A netlist gives the IP core vendor reasonable protection against reverse engineering. See also: integrated circuit layout design protection.
Both netlist and synthesizable cores are called "soft cores", as both allow a synthesis, placement and routing design flow.

Hard cores

Hard cores are defined as IP cores that cannot be modified and are thus "hard", analogous to the etymology of hardware and software. By the nature of their low-level representation, hard cores offer better predictability of chip performance in terms of timing performance and area.
Analog and mixed-signal logic are generally defined as a lower-level, physical description. Hence, analog IP are provided to chip makers in transistor-layout format. Digital IP cores are sometimes offered in layout format as well.
Such cores, whether analog or digital, are called "hard cores", because the core's application function cannot be meaningfully modified by chip designers. Transistor layouts must obey the target foundry's process design rules, and hence, hard cores delivered for one foundry's process cannot be easily ported to a different process or foundry. Merchant foundry operators offer a variety of hard-macro IP functions built for their own foundry process, helping to ensure customer lock-in.
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Licensed functionality

Many of the best known IP cores are soft microprocessor designs. Their instruction sets vary from small 8-bit processors, such as the 8051 and PIC to 32-bit and 64-bit processors such as the ARM architectures or MIPS architectures. Such processors form the "brains" of many embedded systems. They are usually RISC instruction sets rather than CISC instruction sets like x86 because less logic is required and therefore designs are smaller. Further, x86 leaders Intel and AMD heavily protect their processor designs' intellectual property and don't use this business model for their x86-64 lines of microprocessors.
IP cores are also licensed for a variety of peripheral controllers such as for PCI Express, SDRAM, Ethernet, LCD display, AC'97 audio, and USB. Many of those interfaces require digital logic as well as analog IP cores to drive and receive high speed, high voltage, or high impedance signals outside of the chip.
"Hardwired" digital logic IP cores are also licensed for fixed functions such as MP3 audio decode, 3D GPU, digital video encode/decode, and other DSP functions such as FFT, DCT, or Viterbi coding.

Vendors

IP core developers and licensors range in size from individuals to multi billion-dollar corporations. Developers, as well as their chip making customers are located throughout the world.
Silicon Intellectual Property is a business model for a semiconductor company where the company licenses its technology to a customer as intellectual property. This is a type of fabless semiconductor company which doesn't provide physical chips to its customers but merely facilitates the customer's development of chips by offering certain functional blocks. Typically, the customers are semiconductor companies or module developers with in-house semiconductor development. A company wishing to fabricate a complex device may purchase the rights to use another company's well-tested functional blocks such as a microprocessor, instead of developing their own design which would take additional time and cost.
The Silicon IP industry is fairly new but with stable growth. The most successful Silicon IP companies, often referred to as the Star IP, include ARC International, ARM Holdings, Rambus and MIPS Technologies. Gartner Group estimated the total value of sales related to silicon intellectual property at US $1.5 billion in 2005, with annual growth expected around 30%.

IP hardening

IP hardening is a process to re-use proven design, and generate fast time-to-market, low-risk-in-fabrication solutions to provide Intellectual property of design cores.
For example, a digital signal processor is developed from soft cores of RTL format, and it can be targeted to various technologies or different foundries to yield different implementations. The process of IP hardening is from soft core to generate re-usable hard cores. A main advantage of such hard IP is its predictable characteristics as the IP has been pre-implemented, while it offers flexibility of soft cores. It might come with a set of models for simulations or verifications.
The effort input to harden the soft IP means quality of the target technology, goals of design and the methodology employed. The hard IP has been proven in the target technology and application. E.g. the hard core in GDS II format is said to clean in DRC, and LVS. I.e. that can pass all the rules required for manufacturing by the specific foundry.

Free and open-source

Beginning around 2000, OpenCores.org has offered a wide variety of designs, mostly written in VHDL and Verilog. All of these cores are provided under some free and open-source software-license, e.g. GNU General Public License or BSD-like licenses.
Since 2010 initiatives such as RISC-V have caused a massive expansion in the number of IP cores available and this has helped to increase collaboration in developing secure and efficient designs.

Aggregators

Intellectual property aggregators keep catalogs of cores from multiple vendors and provide search and marketing services to their customers.