SuperSPARC
The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contained 3.1 million transistors. It was fabricated by Texas Instruments at Miho, Japan in a 0.8 micrometre triple-metal BiCMOS process.
There were two derivatives of the SuperSPARC: the SuperSPARC+ and SuperSPARC-II. The SuperSPARC+ was developed to remedy some of the design flaws that limited the SuperSPARC's clock frequency and thus performance. The SuperSPARC-II, introduced in 1994, was a major revision with improvements that enabled the microprocessor to reach 85 MHz in desktop systems and 90 MHz in the more heavily cooled SPARCserver-1000E.
The SuperSPARC-II was replaced in 1995 by the 64-bit UltraSPARC, an implementation of the 64-bit SPARC V9 ISA.Models
SuperSPARC (Viking)
- * SM20: 1 CPU, no L2-Cache, 33 MHz, Bus: 33 MHz
- * SM21: 1 CPU, 1 MB L2-Cache, 33 MHz, Bus: 33 MHz
- * SM30: 1 CPU, no L2-Cache, 36 MHz, Bus: 36 MHz
- * SM40: 1 CPU, no L2-Cache, 40 MHz, Bus: 40 MHz
- * SM41: 1 CPU, 1 MB L2-Cache, 40.3 MHz, Bus: 40 MHz
- * SM50: 1 CPU, no L2-Cache, 50 MHz, Bus: 50 MHz
- * SM51: 1 CPU, 1 MB L2-Cache, 50 MHz, Bus: 40 MHz
- * SM51-2: 1 CPU, 2 MB L2-Cache, 50 MHz, Bus: 40 MHz
- * SM52: 2 CPU, 1 MB L2-Cache, 45 MHz, Bus: 40 MHz
- * SM52X: 2 CPU, 1 MB L2-Cache, 50 MHz, Bus: 40 MHz
- * SM61: 1 CPU, 1 MB L2-Cache, 60 MHz, Bus: 50/55 MHz
- * SM61-2: 1 CPU, 2 MB L2-Cache, 60 MHz, Bus: 50/55 MHz
SuperSPARC II (Voyager)
- * SM71: 1 CPU, 1 MB L2-Cache, 75 MHz, Bus: 50 MHz
- * SM81: 1 CPU, 1 MB L2-Cache, 85 MHz, Bus: 50 MHz
- * SM81-2: 1 CPU, 2 MB L2-Cache, 85 MHz, Bus: 50/55 MHz
- * SM91-2: 1 CPU, 2 MB L2-Cache, 90 MHz, Bus: 50 MHz
