TopoR


TopoR is an EDA program developed and maintained by the Russian company Eremex. It is dedicated to laying out a printed circuit board. The current version is 6.3.17875 as of 2017-09-20.
It features a powerful autorouter and a set of tools intended to reduce the amount of effort needed for manual routing of a PCB. The most recognizable feature of TopoR is the absence of preferred routing directions, which results in unusual looking PCBs.

History

Work on a flexible topological router began in 1988, when
1996 saw the release of the first version of a topological router that actually came to be used by industrial enterprises. In 2002, the FreeStyle Router by Диал Инжиниринг ran under DOS and successfully routed dual-layer boards, interfacing with P-CAD. This early router showed the advantages of an innovative approach to routing and high efficiency of the models, algorithms, and software implementation. A 1.44 MB floppy disk was enough for the program and accompanying examples. The company also announced plans to commercially release a FreeStyle Suite for Windows later the year. The last version of FSR for DOS, consisting of the router named SpeedWay and the layout editor named FreeStyle was version 1.6 as of 2003-09-26/2003-11-01.
The first Windows version of the topological router was released in 2001 and renamed to TopoR. TopoR 1.03 was available on 2003-09-26 and distributed through ElekTrade. The program routed not only dual-layer but also multi-layer printed circuit boards. TopoR was developed by a group called the FreeStyleTeam, supervised by Sergey J. Luzin, with Oleg B. Polubasov as initial FSR developer, as well as Paul I. Dmitriev, Gevorg S. Petrosyan, Michael S. Luzin and Andrew A. Lysenko. Version 3.0 was released in 2006. The software was commercially distributed by Prosoft Spb. in 2007. TopoR 4.0 added support to import/export DSN design and SES session files. Since TopoR 4.1 the software is further developed and maintained by Eremex, Ltd.

Features

TopoR can be used as an external autorouter for third-party layout editors or in conjunction with Eremex's own schematic capture and layout editor Delta Design. TopoR imports input in Delta Design's FST format, as Specctra-/ELECTRA-compatible DSN design files, or in P-CAD PCB ASCII, PADS PCB ASCII, or EAGLE BRD XML formats. The resulting boards can be exported into Specctra/ELECTRA SES session files, DXF, Gerber, P-CAD PCB ASCII, PADS PCB ASCII.
Routing of the wiring topology is done automatically and flexibly; angles are not limited to 90° and 45°.
Efficient use of PCB space and absence of preferred routing directions in layers considerably reduces electromagnetic crosstalk.
TopoR routes all connections, even if this entails violating design constraints. Such violations can be automatically corrected later.
When objects are moved around, wire length and shape are optimized automatically with appropriate clearance.
The user is free to choose from two ways to calculate the wire shape: with or without arcs. The first method involves wires consisting of lines only. The other makes wires keep appropriate clearance when circling around pads; it consists of arcs and lines.
TopoR simultaneously optimizes several alternative variants of the layout. Variants with the worst parameters will be removed.
TopoR has an automatic component placement feature. The procedure can be used both for all components of the board and only for components in a specific area. It is not comparable to the quality of the manual placement, but it can be used as a preparation step for manual placement.
The minimum and desired clearances for each net can be specified.
TopoR automatically supports trace necking, that is, it reduces the width of a wire that approaches a narrow pad, or when it passes through bottlenecks.
Wire-to-pad transitions use teardrop-style smoothing. The use of this procedure at the design stage helps avoid violations in design-rule checking when teardrops are added in the CAM editor.
TopoR can recognize ball grid array component areas and apply a special strategy for routing them. This helps reduce the number of vias, the density of connections, and in some cases the number of routing layers.
A special algorithm is used for routing single-layer boards minimizing the number of interlayer junctions or to find a single-layer routing.

Similar solutions

The layout program PCB of the gEDA suite includes a similar topological autorouter named Toporouter, which was written by Anthony Blake in a Google-funded open source project mentored by DJ Delorie in 2008. It is mostly based on an implementation of the algorithms described in Tal Dayan's 1997 PhD thesis, "Rubberband based topological router". This router has meanwhile been adapted for use with the open-source KiCad project as well.