was renamed VIA C3 with the switch to the advanced "Samuel 2" core. The addition of an on-die L2 cache improved performance somewhat. As it was not built upon Cyrix technology at all, the new name was just a logical step. To improve power consumption and reduce manufacturing costs, Samuel 2 was produced with 150 nm process technology. The VIA C3 processor continued an emphasis on minimizing power consumption with the next die shrink to a mixed 130/150 nm process. "Ezra" and "Ezra-T" were only new revisions of the "Samuel 2" core with some minor modifications to the bus protocol of "Ezra-T" to match compatibility with Intel's Pentium III "Tualatin" cores. VIA enjoyed the lowest power usage in the x86 CPU market for several years. Performance, however, fell behind due to the lack of improvements to the design. Uniquely, the retail C3 CPU shipped inside a decorative tin.
Nehemiah cores
The "Nehemiah" was a major core revision. At the time, VIA's marketing efforts did not fully reflect the changes that had taken place. The company addressed numerous design shortcomings of the older cores, including the half-speed FPU. The number of pipeline stages was increased from 12 to 16, to allow for continued increases in clock speed. Additionally, it implemented the cmov instruction, making it a 686-class processor. The Linux kernel refers to this core as the C3-2. It also removes 3DNow! instructions in favour of implementing SSE. However, it was still based upon the aging Socket 370, running the single data ratefront side bus at just 133 MHz. Because the embedded system marketplace prefers low-power, low-cost CPU designs, VIA began targeting this segment more aggressively because the C3 fit those traits rather well. Centaur Technology concentrated on adding features attractive to the embedded marketplace. An example built into the first "Nehemiah" core were the twin hardware random number generators. The "Nehemiah+" revision brought a few more advancements, including a high-performance AES encryption engine along with a notably small ball grid array chip package the size of a US 1 cent coin. At the time VIA also boosted the FSB to 200 MHz and introduced new chipsets such as the CN400 to support it. Obviously the new 200 MHz FSB chips are only available in BGA packages as they are not compatible with existing Socket 370 motherboards. When this architecture was marketed it was often referred to as the "VIA C5".
Technical information
Comparative die size
Processor
Secondary Cache
Die size 180 nm
Die size 150 nm
Die size 130 nm
Die size 90 nm
C3 Samuel
N/A
?
N/A
N/A
N/A
C3 Samuel 2
64
N/A
?
N/A
N/A
C3 Ezra
64
N/A
N/A
52
N/A
C3 Nehemiah
64
N/A
N/A
52
N/A
C7 Esther
128
N/A
N/A
N/A
30
Athlon XP
256
N/A
N/A
84
N/A
Athlon 64
512
N/A
N/A
144
84
Pentium M
2048
N/A
N/A
N/A
84
P4 Northwood
512
N/A
N/A
146
N/A
P4 Prescott
1024
N/A
N/A
N/A
110
Design methodology
While slower than x86 CPUs being sold by AMD and Intel, both in absolute terms and on a clock-for-clock basis, VIA's chips were much smaller, cheaper to manufacture, and lower power. This made them highly attractive in the embedded marketplace. This has also enabled VIA to continue to scale the frequencies of their chips with each manufacturing process die shrink, while competitive products from Intel encountered severe thermal management issues, although the later Intel Core generation of chips were substantially cooler.
C3
Because memory performance is the limiting factor in many benchmarks, VIA processors implement large primary caches, large TLBs, and aggressive prefetching, among other enhancements. While these features are not unique to VIA, memory access optimization is one area where they have not dropped features to save die space.
Clock frequency is in general terms favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios.
The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Several frequently used instructions require fewer pipeline clocks than on other x86 processors.
Infrequently used x86 instructions are implemented in microcode and emulated. This saves die space and reduces power consumption. The impact upon the majority of real-world application scenarios is minimized.
These design guidelines are derivative from the original RISC advocates, who stated a smaller set of instructions, better optimized, would deliver faster overall CPU performance. As it makes heavy use of memory operands, both as source and destination, the C3 design itself cannot qualify as RISC however.
Business
Contracts
VIA's embedded platform products have reportedly been adopted in Nissan's car series, the Lafesta, Murano, and Presage. These and other high volume industrial applications are starting to generate big profits for VIA as the small form factor and low power advantages close embedded deals.
Legal issues
On the basis of the IDT Centaur acquisition, VIA appears to have come into possession of at least three patents, which cover key aspects of processor technology used by Intel. On the basis of the negotiating leverage these patents offered, in 2003 VIA arrived at an agreement with Intel that allowed for a ten-year patent cross license, enabling VIA to continue to design and manufacture x86 compatible CPUs. VIA was also granted a three-year period of grace in which it could continue to use Intel socket infrastructure.
