AArch64 or ARM64 is the 64-bit extension of the ARM architecture. It was first introduced with the ARMv8-A architecture.
ARMv8-A
Announced in October 2011, ARMv8-A represents a fundamental change to the ARM architecture. It adds an optional 64-bit architecture, named "AArch64", and the associated new "A64" instruction set. AArch64 provides user-space compatibility with ARMv7-A, the 32-bit architecture, therein referred to as "AArch32" and the old 32-bit instruction set, now named "A32". The Thumb instruction set is referred to as "T32" and has no 64-bit counterpart. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor. ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012. Apple was the first to release an ARMv8-A compatible core in a consumer product. AppliedMicro, using an FPGA, was the first to demo ARMv8-A. The first ARMv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it will run only in AArch32 mode. To both AArch32 and AArch64, ARMv8-A makes VFPv3/v4 and advanced SIMD standard. It also adds cryptography instructions supporting AES, SHA-1/SHA-256 and finite field arithmetic.
AArch64 features
New instruction set, A64
* Has 31 general-purpose 64-bit registers.
* Has dedicated zero or stack pointer register.
* The program counter is no longer directly accessible as a register.
* Instructions are still 32 bits long and mostly the same as A32.
* AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.
A new exception system
* Fewer banked registers and modes.
Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension, which was designed to be easily extended to 64-bit.
AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMV8-A. AArch64 is not included in ARMv8-R or ARMv8-M, because they are both 32-bit architectures.
ARMv8.1-A
In December 2014, ARMv8.1-A, an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation. Instruction set enhancements included the following:
A set of AArch64 atomic read-write instructions.
Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations:
* Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half.
* Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half.
* The instructions are added in vector and scalar forms.
A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions.
The optional CRC instructions in v8.0 become a requirement in ARMv8.1.
Enhancements for the exception model and memory translation system included the following:
A new Privileged Access Never state bit provides control that prevents privileged access to user data unless explicitly enabled.
An increased VMID range for virtualization; supports a larger number of virtual machines.
Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism.
The Virtualization Host Extensions. These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems. The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification.
A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS.
The Scalable Vector Extension is "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of high-performance computing scientific workloads. The specification allows for variable vector lengths to be implemented from 128 to 2048 bits. The extension is completementary to, and does not replace, the NEON extensions. A 512-bit SVE variant has already been implemented on the Fugaku supercomputer using the Fujitsu A64FXARM processor. It aims to be the world's highest-performing supercomputer with "the goal of beginning full operations around 2021." SVE is supported by the GCC compiler, with GCC 8 supporting automatic vectorization and GCC 10 supporting C intrinsics. As of July 2020, LLVM and clang support C intrinsics.
ARMv8.3-A
In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories:
Pointer authentication ; mandatory extension to the architecture.
SIMD matrix manipulation instructions, BFDOT, BFMMLA, BFMLAL and BFCVT
enhancements for virtualization, system management and security
For example, Fine grained traps, Wait-for-Event instructions, EnhancedPAC2 and FPAC. The Bfloat16 extensions for SVE and [|Neon] are mainly for deep learning use.
Future ARM architecture features
In May 2019, ARM announced their upcoming Scalable Vector Extension 2 and Transactional Memory Extension.
Scalable Vector Extension 2 (SVE2)
SVE2 builds on SVE's scalable vectorization for increased fine-grain Data Level Parallelism, to allow more work done per instruction. SVE2 aims to bring these benefits to a wider range of software including DSP and multimedia SIMD code that currently use Neon. The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support SVE2.
Transactional Memory Extension (TME)
Following the x86 extensions, TME brings support for Hardware Transactional Memory and Transactional Lock Elision. TME aims to bring scalable concurrency to increase coarse-grained Thread Level Parallelism, to allow more work done per thread. The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support TME.
