ARM Cortex-A77


The ARM Cortex-A77 is a microarchitecture implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM announced an increase of 23% and 35% in integer and floating point performance, respectively. Memory bandwidth increased 15% relative to the A76.

Design

The Cortex-A77 serves as the successor of the Cortex-A76. The Cortex-A77 is a 4-wide decode out-of-order superscalar design with a new 1.5K macro-OP cache. It can fetch 4 instructions and 6 Mops per cycle. And rename and dispatch 6 Mops, and 13 µops per cycle. The out-of-order window size has been increased to 160 entries. The backend is 12 execution ports with a pipeline depth of 13 stages and the execution latencies of 10 stages.
The core supports unprivileged 32-bit applications, but privileged applications must utilize the 64-bit ARMv8-A ISA. It also supports Load acquire instructions, Dot Product instructions, and PSTATE Speculative Store Bypass Safe bit instructions.
The Cortex-A77 supports ARM's DynamIQ technology, and is expected to be used as high-performance cores in combination with Cortex-A55 power-efficient cores.

Licensing

The Cortex-A77 is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores into one die constituting a system on a chip.

Usage

Derivatives by the name of Kryo 585 and Kryo 560, is used in the Snapdragon 865 and Snapdragon 690.
Also used in the Exynos 980 and Exynos 880. And the MediaTek Dimensity 1000, 1000L and 1000+.