ARM Cortex-M


The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. These cores are optimized for low-cost and energy-efficient microcontrollers, which have been embedded in tens of billions of consumer devices. The cores consist of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55. The Cortex-M4 / M7 / M33 / M35P / M55 cores have an FPU silicon option, and when included in the silicon these cores are sometimes known as "Cortex-Mx with FPU" or "Cortex-MxF", where 'x' is the core number.

Overview

The ARM Cortex-M family are ARM microprocessor cores which are designed for use in microcontrollers, ASICs, ASSPs, FPGAs, and SoCs. Cortex-M cores are commonly used as dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management controllers, I/O controllers, system controllers, touch screen controllers, smart battery controllers, and sensors controllers.
Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward. Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from 32-bit math operations, and replacing older legacy ARM cores such as ARM7 and ARM9.

License

neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. Arm offers a variety of licensing terms, varying in cost and deliverables. To all licensees, Arm provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization

Integrated Device Manufacturers receive the ARM Processor IP as synthesizable RTL. In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.
Some of the silicon options for the Cortex-M cores are:
ARM CoreCortex
M0		Cortex
M0+		Cortex
M1		Cortex
M3		Cortex
M4		Cortex
M7		Cortex
M23		Cortex
M33		Cortex
M35P
SysTick 24-bit TimerOptional
Optional
Optional
Optional
Single-cycle I/O portOptionalOptional
Bit-Band memory*OptionalOptionalOptional
Memory Protection
Unit 		Optional
Optional
Optional
Optional
Optional
Optional
Optional
*
Security Attribution
Unit and
Stack Limits		Optional
Optional
Optional
*
Instruction TCMOptionalOptional
Data TCMOptionalOptional
Instruction CacheOptionalOptional
Data CacheOptional
Vector Table Offset
Register 		Optional
Optional
Optional
Optional
Optional
Optional

Additional silicon options:
The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture, the Cortex-M3 implements the ARMv7-M architecture, the Cortex-M4 / Cortex-M7 implements the ARMv7E-M architecture, the Cortex-M23 / M33 / M35P implement the ARMv8-M architecture, and the Cortex-M55 implements the ARMv8.1-M architecture. The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-M3 / Cortex-M4 / Cortex-M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / Cortex-M7 / Cortex-M33 / Cortex-M35P. Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures; the legacy 32-bit ARM instruction set isn't supported.
All Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply. The Cortex-M0 / Cortex-M0+ / Cortex-M1 / Cortex-M23 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family.
The Cortex-M0 / M0+ / M1 include Thumb-1 instructions, except new instructions which were added in ARMv7-M architecture. The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions. The Cortex-M3 / M4 / M7 / M33 / M35P have all base Thumb-1 and Thumb-2 instructions. The Cortex-M3 adds three Thumb-1 instructions, all Thumb-2 instructions, hardware integer divide, and saturation arithmetic instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit. The Cortex-M7 adds an optional double-precision FPU. The Cortex-M23 / M33 add TrustZone instructions.
Arm CoreCortex
M0		Cortex
M0+		Cortex
M1		Cortex
M3		Cortex
M4		Cortex
M7		Cortex
M23		Cortex
M33		Cortex
M35P		Cortex
M55
ARM architectureARMv6-MARMv6-MARMv6-MARMv7-MARMv7E-MARMv7E-MARMv8-M
Baseline		ARMv8-M
Mainline		ARMv8-M
Mainline		Armv8.1-M
Computer architectureVon NeumanVon NeumannVon NeumannHarvardHarvardHarvardVon NeumannHarvardHarvardHarvard
Instruction pipeline3 stages2 stages3 stages3 stages3 stages6 stages2 stages3 stages3 stages4 to 5 stages
Thumb-1 instructionsMostMostMostMost
Thumb-2 instructionsSomeSomeSomeSome
Multiply instructions
32x32 = 32-bit result
Multiply instructions
32x32 = 64-bit result
Divide instructions
32/32 = 32-bit quotient
Saturated instructionsSome
DSP instructionsOptionalOptionalOptional
Single-Precision
Floating-point instructions		OptionalOptionalOptionalOptionalOptional
Double-Precision
Floating-point instructions		OptionalOptional
Half-Precisions Optional
TrustZone instructionsOptionalOptionalOptionalOptional
Co-processor instructionsOptionalOptionalOptional
Helium technologyOptional
Interrupt latency
16 cycles15 cycles23 for NMI
26 for IRQ		12 cycles12 cycles12 cycles15 no security ext
27 security ext		TBDTBDTBD

GroupInstr
bits		InstructionsCortex
M0,M0+,M1		Cortex
M3		Cortex
M4		Cortex
M7		Cortex
M23		Cortex
M33,M35P		Cortex
M55
16ADC, ADD, ADR, AND, ASR, B, BIC, BKPT, BLX, BX, CMN, CMP, CPS, EOR, LDM, LDR, LDRB, LDRH, LDRSB, LDRSH, LSL, LSR, MOV, MUL, MVN, NOP, ORR, POP, PUSH, REV, REV16, REVSH, ROR, RSB, SBC, SEV, STM, STR, STRB, STRH, SUB, SVC, SXTB, SXTH, TST, UXTB, UXTH, WFE, WFI, YIELD
16CBNZ, CBZ
16IT
32BL, DMB, DSB, ISB, MRS, MSR
32SDIV, UDIV
32ADC, ADD, ADR, AND, ASR, B, BFC, BFI, BIC, CDP, CLREX, CLZ, CMN, CMP, DBG, EOR, LDC, LDM, LDR, LDRB, LDRBT, LDRD, LDREX, LDREXB, LDREXH, LDRH, LDRHT, LDRSB, LDRSBT, LDRSH, LDRSHT, LDRT, LSL, LSR, MCR, MCRR, MLA, MLS, MOV, MOVT, MRC, MRRC, MUL, MVN, NOP, ORN, ORR, PLD, PLDW, PLI, POP, PUSH, RBIT, REV, REV16, REVSH, ROR, RRX, RSB, SBC, SBFX, SEV, SMLAL, SMULL, SSAT, STC, STM, STR, STRB, STRBT, STRD, STREX, STREXB, STREXH, STRH, STRHT, STRT, SUB, SXTB, SXTH, TBB, TBH, TEQ, TST, UBFX, UMLAL, UMULL, USAT, UXTB, UXTH, WFE, WFI, YIELD
DSP32PKH, QADD, QADD16, QADD8, QASX, QDADD, QDSUB, QSAX, QSUB, QSUB16, QSUB8, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSAX, SHSUB16, SHSUB8, SMLABB, SMLABT, SMLATB, SMLATT, SMLAD, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, SMLAWB, SMLAWT, SMLSD, SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD, SMULBB, SMULBT, SMULTT, SMULTB, SMULWT, SMULWB, SMUSD, SSAT16, SSAX, SSUB16, SSUB8, SXTAB, SXTAB16, SXTAH, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSAX, UHSUB16, UHSUB8, UMAAL, UQADD16, UQADD8, UQASX, UQSAX, UQSUB16, UQSUB8, USAD8, USADA8, USAT16, USAX, USUB16, USUB8, UXTAB, UXTAB16, UXTAH, UXTB16Optional
SP Float32VABS, VADD, VCMP, VCMPE, VCVT, VCVTR, VDIV, VLDM, VLDR, VMLA, VMLS, VMOV, VMRS, VMSR, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VPOP, VPUSH, VSQRT, VSTM, VSTR, VSUBOptionalOptionalOptionalOptional
DP Float32VCVTA, VCVTM, VCVTN, VCVTP, VMAXNM, VMINNM, VRINTA, VRINTM, VRINTN, VRINTP, VRINTR, VRINTX, VRINTZ, VSELOptionalOptional
TrustZone16BLXNS, BXNSOptionalOptionalOptional
TrustZone32SG, TT, TTT, TTA, TTATOptionalOptionalOptional
Co-processor16CDP, CDP2, MCR, MCR2, MCRR, MCRR2, MRC, MRC2, MRRC, MRRC2OptionalOptional

The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:
The capabilities of the 32-bit ARM instruction set is duplicated in many ways by the Thumb-1 and Thumb-2 instruction sets, but some ARM features don't have a similar feature:
The 16-bit Thumb-1 instruction set has evolved over time since it was first released in the legacy ARM7T cores with the ARMv4T architecture. New Thumb-1 instructions were added as each legacy ARMv5 / ARMv6 / ARMv6T2 architectures were released. Some 16-bit Thumb-1 instructions were removed from the Cortex-M cores:
The Cortex-M0 core is optimized for small silicon die size and use in the lowest price chips.
Key features of the Cortex-M0 core are:
Silicon options:
The following microcontrollers are based on the Cortex-M0 core:
The following chips have a Cortex-M0 as a secondary core:
The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing the use of the same compiler and debug tools. The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage. In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer which provides a simple instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the memory protection unit and the vector table relocation.
Key features of the Cortex-M0+ core are:
Silicon options:
The following microcontrollers are based on the Cortex-M0+ core:
The following chips have a Cortex-M0+ as a secondary core:
The smallest ARM microcontrollers are of the Cortex-M0+ type.

World's smallest computer

On 21 June 2018, the "world's smallest computer'", or computer device was announced based on the ARM Cortex-M0+ by University of Michigan researchers at the 2018 Symposia on VLSI Technology and Circuits with the paper "A 0.04mm3 16nW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement." The device is 1/10th the size of IBM's previously claimed world-record-sized computer from months back in March 2018, which is smaller than a grain of salt.

Cortex-M1

The Cortex-M1 is an optimized core especially designed to be loaded into FPGA chips.
Key features of the Cortex-M1 core are:
Silicon options:
The following vendors support the Cortex-M1 as soft-cores on their FPGA chips:
Key features of the Cortex-M3 core are:
Silicon options:
The following microcontrollers are based on the Cortex-M3 core:
The following chips have a Cortex-M3 as a secondary core:
The following FPGAs include a Cortex-M3 core:
The following vendors support the Cortex-M3 as soft-cores on their FPGA chips:
Conceptually the Cortex-M4 is a Cortex-M3 plus DSP instructions, and optional floating-point unit. A core with an FPU is known as Cortex-M4F.
Key features of the Cortex-M4 core are:
Silicon options:
The following microcontrollers are based on the Cortex-M4 core:
The following microcontrollers are based on the Cortex-M4F core:
The following chips have either a Cortex-M4 or M4F as a secondary core:
The Cortex-M7 is a high-performance core with almost double the power efficiency of the older Cortex-M4. It features a 6-stage superscalar pipeline with branch prediction and an optional floating-point unit capable of single-precision and optionally double-precision operations. The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses. If a core contains an FPU, it is known as a Cortex-M7F, otherwise it is a Cortex-M7.
Key features of the Cortex-M7 core are:
Silicon options:
The following microcontrollers are based on the Cortex-M7 core:
The Cortex-M23 core was announced in October 2016 and based on the newer ARMv8-M architecture that was previously announced in November 2015. Conceptually the Cortex-M23 is similar to a Cortex-M0+ plus integer divide instructions and TrustZone security features, and also has a 2-stage instruction pipeline.
Key features of the Cortex-M23 core are:
Silicon options:
The following microcontrollers are based on the Cortex-M23 core:
The Cortex-M33 core was announced in October 2016 and based on the newer ARMv8-M architecture that was previously announced in November 2015. Conceptually the Cortex-M33 is similar to a cross of Cortex-M4 and Cortex-M23, and also has a 3-stage instruction pipeline.
Key features of the Cortex-M33 core are:
Silicon options:
The following microcontrollers are based on the Cortex-M33 core:
The Cortex-M35P core was announced in May 2018. It is conceptually a Cortex-M33 core with a new instruction cache, plus new tamper-resistant hardware concepts borrowed from the ARM SecurCore family, and configurable parity and ECC features.
Limited public information is currently available for the Cortex-M35P until its Technical Reference Manual is released.

Chips

The following microcontrollers are based on the Cortex-M35P core:
The Cortex-M55 core was announced in February 2020 and is based on the Armv8.1-M architecture that was previously announced in February 2019. It also has a 4-stage instruction pipeline.
Key features of the Cortex-M55 core include:
Silicon options:
The following microcontrollers are based on the Cortex-M55 core:

Documentation

The documentation for ARM chips is extensive. In the past, 8-bit microcontroller documentation would typically fit in a single document, but as microcontrollers have evolved, so has everything required to support them. A documentation package for ARM chips typically consists of a collection of documents from the IC manufacturer as well as the CPU core vendor.
A typical top-down documentation tree is:
;Documentation tree
  1. IC manufacturer website.
  2. IC manufacturer marketing slides.
  3. IC manufacturer datasheet for the exact physical chip.
  4. IC manufacturer reference manual that describes common peripherals and aspects of a physical chip family.
  5. ARM core website.
  6. ARM core generic user guide.
  7. ARM core technical reference manual.
  8. ARM architecture reference manual.
IC manufacturers have additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See [|External links] section for links to official Arm documents.