Binary multiplier
A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders.
A variety of :Category:computer arithmetic|computer arithmetic techniques can be used to implement a digital multiplier. Most techniques involve computing a set of partial products, and then summing the partial products together. This process is similar to the method taught to primary schoolchildren for conducting long multiplication on base-10 integers, but has been modified here for application to a base-2 numeral system.
History
Between 1947-1949 Arthur Alec Robinson worked for English Electric Ltd, as a student apprentice, and then as a development engineer. Crucially during this period he studied for a PhD degree at the University of Manchester, where he worked on the design of the hardware multiplier for the early Mark 1 computer.However, until the late 1970s, most minicomputers did not have a multiply instruction, and so programmers used a "multiply routine"
which repeatedly shifts and accumulates partial results,
often written using loop unwinding. Mainframe computers had multiply instructions, but they did the same sorts of shifts and adds as a "multiply routine".
Early microprocessors also had no multiply instruction. Though the multiply instruction is usually associated with the 16-bit microprocessor generation,
at least two "enhanced" 8-bit micro have a multiply instruction: the Motorola 6809, introduced in 1978, and Intel MCS-51 family, developed in 1980, and later the modern Atmel AVR 8-bit microprocessors present in the ATMega, ATTiny and ATXMega microcontrollers.
As more transistors per chip became available due to larger-scale integration, it became possible to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time.
Because some common digital signal processing algorithms spend most of their time multiplying, digital signal processor designers sacrifice considerable chip area in order to make the multiply as fast as possible; a single-cycle multiply–accumulate unit often used up most of the chip area of early DSPs.
Basics
The method taught in school for multiplying decimal numbers is based on calculating partial products, shifting them to the left and then adding them together. The most difficult part is to obtain the partial products, as that involves multiplying a long number by one digit :x 456
738
615
+ 492
56088
56088
Binary numbers
A binary computer does exactly the same multiplication as decimal numbers do, but with binary numbers. In binary encoding each long number is multiplied by one digit, and that is much easier than in decimal, as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two binary numbers comes down to calculating partial products, shifting them left, and then adding them together :1011
x 1110
0000
1011
1011
+ 1011
10011010
This is much simpler than in the decimal system, as there is no table of multiplication to remember: just shifts and adds.
This method is mathematically correct and has the advantage that a small CPU may perform the multiplication by using the shift and add features of its arithmetic logic unit rather than a specialized circuit. The method is slow, however, as it involves many intermediate additions. These additions are time-consuming. Faster multipliers may be engineered in order to do fewer additions; a modern processor can multiply two 64-bit numbers with 6 additions, and can do several steps in parallel.
The second problem is that the basic school method handles the sign with a separate rule. Modern computers embed the sign of the number in the number itself, usually in the two's complement representation. That forces the multiplication process to be adapted to handle two's complement numbers, and that complicates the process a bit more. Similarly, processors that use ones' complement, sign-and-magnitude, IEEE-754 or other binary representations require specific adjustments to the multiplication process.
Unsigned numbers
For example, suppose we want to multiply two unsigned eight bit integers together: a and b. We can produce eight partial products by performing eight one-bit multiplications, one for each bit in multiplicand a:p1 = a × b = & b
p2 = a × b = & b
p3 = a × b = & b
p4 = a × b = & b
p5 = a × b = & b
p6 = a × b = & b
p7 = a × b = & b
where
To produce our product, we then need to add up all eight of our partial products, as shown here:
p0 p0 p0 p0 p0 p0 p0 p0
+ p1 p1 p1 p1 p1 p1 p1 p1 0
+ p2 p2 p2 p2 p2 p2 p2 p2 0 0
+ p3 p3 p3 p3 p3 p3 p3 p3 0 0 0
+ p4 p4 p4 p4 p4 p4 p4 p4 0 0 0 0
+ p5 p5 p5 p5 p5 p5 p5 p5 0 0 0 0 0
+ p6 p6 p6 p6 p6 p6 p6 p6 0 0 0 0 0 0
+ p7 p7 p7 p7 p7 p7 p7 p7 0 0 0 0 0 0 0
-------------------------------------------------------------------------------------------
P P P P P P P P P P P P P P P P
In other words, P is produced by summing p0, p1 << 1, p2 << 2, and so forth, to produce our final unsigned 16-bit product.
Signed integers
If b had been a signed integer instead of an unsigned integer, then the partial products would need to have been sign-extended up to the width of the product before summing. If a had been a signed integer, then partial product p7 would need to be subtracted from the final sum, rather than added to it.The above array multiplier can be modified to support two's complement notation signed numbers by inverting several of the product terms and inserting a one to the left of the first partial product term:
1 ~p0 p0 p0 p0 p0 p0 p0 p0
~p1 +p1 +p1 +p1 +p1 +p1 +p1 +p1 0
~p2 +p2 +p2 +p2 +p2 +p2 +p2 +p2 0 0
~p3 +p3 +p3 +p3 +p3 +p3 +p3 +p3 0 0 0
~p4 +p4 +p4 +p4 +p4 +p4 +p4 +p4 0 0 0 0
~p5 +p5 +p5 +p5 +p5 +p5 +p5 +p5 0 0 0 0 0
~p6 +p6 +p6 +p6 +p6 +p6 +p6 +p6 0 0 0 0 0 0
1 +p7 ~p7 ~p7 ~p7 ~p7 ~p7 ~p7 ~p7 0 0 0 0 0 0 0
------------------------------------------------------------------------------------------------------------
P P P P P P P P P P P P P P P P
Where ~p represents the complement of p.
There are many simplifications in the bit array above that are not shown and are not obvious. The sequences of one complemented bit followed by noncomplemented bits are implementing a two's complement trick to avoid sign extension. The sequence of p7 is because we're subtracting this term so they were all negated to start out with. For both types of sequences, the last bit is flipped and an implicit -1 should be added directly below the MSB. When the +1 from the two's complement negation for p7 in bit position 0 and all the -1's in bit columns 7 through 14 are added together, they can be simplified to the single 1 that "magically" is floating out to the left. For an explanation and proof of why flipping the MSB saves us the sign extension, see a computer arithmetic book.
Floating point numbers
A binary floating number contains a sign bit, significant bits and exponent bits. The sign bits of each operand are XOR'd to get the sign of the answer. Then, the two exponents are added to get the exponent of the result. Finally, multiplication of each operand's significand will return the significand of the result. However, if the result of the binary multiplication is higher then the total number of bits for a specific precision, rounding is required and the exponent is changed appropriately.Implementations
The process of multiplication can be split into 3 steps:- generating partial product
- reducing partial product
- computing final product
For speed, shift-and-add multipliers require a fast adder.
A "single cycle" multiplier is pure combinational logic.
In a fast multiplier,
the partial-product reduction process usually contributes the most to the delay, power, and area of the multiplier.
For speed, the "reduce partial product" stages are typically implemented as a carry-save adder composed of compressors and the "compute final product" step is implemented as a fast adder.
Many fast multipliers use full adders as compressors implemented in static CMOS.
To achieve better performance in the same area or the same performance in a smaller area, multiplier designs may use higher order compressors such as 7:3 compressors;
implement the compressors in faster logic ;
connect the compressors in a different pattern; or some combination.