DIMM


A DIMM or dual in-line memory module, commonly called RAM stick, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers. DIMMs began to replace SIMMs as the predominant type of memory module as Intel P5-based Pentium processors began to gain market share.
While the contacts on SIMMs on both sides are redundant, DIMMs have separate electrical contacts on each side of the module. Another difference is that standard SIMMs have a 32-bit data path, while standard DIMMs have a 64-bit data path. Since Intel's Pentium, many processors have a 64-bit bus width, requiring SIMMs installed in matched pairs in order to populate the data bus. The processor would then access the two SIMMs in parallel. DIMMs were introduced to eliminate this disadvantage.

Variants

Variants of DIMM slots support DDR, DDR2, DDR3, DDR4 and DDR5 RAM.
Common types of DIMMs include the following:
70 to 200 pins
201 to 300 pins
On the bottom edge of 168-pin DIMMs there are two notches, and the location of each notch determines a particular feature of the module. The first notch is the DRAM key position, which represents RFU, registered, and unbuffered DIMM types. The second notch is the voltage key position, which represents 5.0 V, 3.3 V, and RFU DIMM types.

DDR DIMMs

, DDR2, DDR3, DDR4 and DDR5 all have different pin counts and/or different notch positions. As of August, 2014, DDR4 SDRAM is a modern emerging type of dynamic random access memory with a high-bandwidth interface, and has been in use since 2013. It is the higher-speed successor to DDR, DDR2 and DDR3. DDR4 SDRAM is neither forward nor backward compatible with any earlier type of random access memory because of different signalling voltages, timings, as well as other differing factors between the technologies and their implementation.

SPD EEPROM

A DIMM's capacity and other operational parameters may be identified with serial presence detect, an additional chip which contains information about the module type and timing for the memory controller to be configured correctly. The SPD EEPROM connects to the System Management Bus and may also contain thermal sensors.

Error correction

DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect which uses an extra byte per 64-bit word. ECC modules usually carry a multiple of 9 instead of a multiple of 8 chips.

Ranking

Sometimes memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called a rank. Ranks that share the same slot, only one rank may be accessed at any given time; it is specified by activating the corresponding rank's chip select signal. The other ranks on the module are deactivated for the duration of the operation by having their corresponding CS signals deactivated. DIMMs are currently being commonly manufactured with up to four ranks per module. Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs.
After a memory word is fetched, the memory is typically inaccessible for an extended period of time while the sense amplifiers are charged for access of the next cell. By interleaving the memory, sequential memory accesses can be performed more rapidly because sense amplifiers have 3 cycles of idle time for recharging, between accesses.
DIMMs are often referred to as "single-sided" or "double-sided" to describe whether the DRAM chips are located on one or both sides of the module's printed circuit board. However, these terms may cause confusion, as the physical layout of the chips does not necessarily relate to how they are logically organized or accessed.
JEDEC decided that the terms "dual-sided", "double-sided", or "dual-banked" were not correct when applied to registered DIMMs.

Organization

Most DIMMs are built using "×4" or "×8" memory chips with nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in bits.
In the case of "×4" registered DIMMs, the data width per side is 36 bits; therefore, the memory controller needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked. For "×8" registered DIMMs, each side is 72 bits wide, so the memory controller only addresses one side at a time.
The above example applies to ECC memory that stores 72 bits instead of the more common 64. There would also be one extra chip per group of eight, which is not counted.

Speeds

For various technologies, there are certain bus and device clock frequencies that are standardized; there is also a decided nomenclature for each of these speeds for each type.
DIMMs based on Single Data Rate DRAM have the same bus frequency for data, address and control lines. DIMMs based on Double Data Rate DRAM have data but not the strobe at double the rate of the clock; this is achieved by clocking on both the rising and falling edge of the data strobes. Power consumption and voltage gradually became lower with each generation of DDR-based DIMMs.
ChipModuleEffective ClockVoltage
SDR-66PC-6666 MHz3.3 V
SDR-100PC-100100 MHz3.3 V
SDR-133PC-133133 MHz3.3 V

ChipModuleMemory ClockI/O Bus ClockTransfer rateVoltage
DDR-200PC-1600100 MHz100 MHz200 MT/s2.5 V
DDR-266PC-2100133 MHz133 MHz266 MT/s2.5 V
DDR-333PC-2700166 MHz166 MHz333 MT/s2.5 V
DDR-400PC-3200200 MHz200 MHz400 MT/s2.5 V

ChipModuleMemory ClockI/O Bus ClockTransfer rateVoltage
DDR2-400PC2-3200200 MHz200 MHz400 MT/s1.8 V
DDR2-533PC2-4200266 MHz266 MHz533 MT/s1.8 V
DDR2-667PC2-5300333 MHz333 MHz667 MT/s1.8 V
DDR2-800PC2-6400400 MHz400 MHz800 MT/s1.8 V
DDR2-1066PC2-8500533 MHz533 MHz1066 MT/s1.8 V

ChipModuleMemory ClockI/O Bus ClockTransfer rateVoltage
DDR3-800PC3-6400400 MHz400 MHz800 MT/s1.5 V
DDR3-1066PC3-8500533 MHz533 MHz1066 MT/s1.5 V
DDR3-1333PC3-10600667 MHz667 MHz1333 MT/s1.5 V
DDR3-1600PC3-12800800 MHz800 MHz1600 MT/s1.5 V
DDR3-1866PC3-14900933 MHz933 MHz1866 MT/s1.5 V
DDR3-2133PC3-170001066 MHz1066 MHz2133 MT/s1.5 V
DDR3-2400PC3-192001200 MHz1200 MHz2400 MT/s1.5 V

ChipModuleMemory ClockI/O Bus ClockTransfer rateVoltage
DDR4-1600PC4-12800800 MHz800 MHz1600 MT/s1.2 V
DDR4-1866PC4-14900933 MHz933 MHz1866 MT/s1.2 V
DDR4-2133PC4-170001066 MHz1066 MHz2133 MT/s1.2 V
DDR4-2400PC4-192001200 MHz1200 MHz2400 MT/s1.2 V
DDR4-2666PC4-213001333 MHz1333 MHz2666 MT/s1.2 V
DDR4-3200PC4-256001600 MHz1600 MHz3200 MT/s1.2 V

Form factors

Several form factors are commonly used in DIMMs. Single Data Rate Synchronous DRAM DIMMs were primarily manufactured in and heights. When 1U rackmount servers started becoming popular, these form factor registered DIMMs had to plug into angled DIMM sockets to fit in the high box. To alleviate this issue, the next standards of DDR DIMMs were created with a "low profile" height of around. These fit into vertical DIMM sockets for a 1U platform.
With the advent of blade servers, angled slots have once again become common in order to accommodate LP form factor DIMMs in these space-constrained boxes. This led to the development of the Very Low Profile form factor DIMM with a height of around. The DDR3 JEDEC standard for VLP DIMM height is around. These will fit vertically in ATCA systems.
Full-height 240-pin DDR2 and DDR3 DIMMs are all specified at a height of around by standards set by JEDEC. These form factors include 240-pin DIMM, SODIMM, Mini-DIMM and Micro-DIMM.
Full-height 288-pin DDR4 DIMMs are slightly taller than their DDR3 counterparts at. Similarly, VLP DDR4 DIMMs are also marginally taller than their DDR3 equivalent at nearly.
As of Q2 2017, Asus has had a PCI-E based "DIMM.2", which has a similar socket to DDR3 DIMMs and is used to put in a module to connect up to two M.2 NVMe solid-state drives. However, it cannot use common DDR type ram and does not have much support other than Asus.