Goldmont Plus

Design

• Widen previous generation Atom processor back-end pipeline to 4-wide allocation to 4-wide retire, while maintaining 3-wide fetch and decode pipeline.
• Enhanced branch prediction unit.
• 64 KB shared second level pre-decode cache.
• Larger reservation station and re-order buffer entries to support large out-of-order window.
• Wider integer execution unit. New dedicated JEU port with support for faster branch redirection.
• Radix-1024 floating point divider for fast scalar/packed single, double and extended precision floating point divides.
• Improved AES-NI instruction latency and throughput.
• Larger load and store buffers. Improved store-to-load forwarding latency store data from register.
• Shared instruction and data second level TLB. Paging Cache Enhancements.
• Modular system design with four cores sharing up to 4 MB L2 cache.
• Support for Read Processor ID new instruction.

  Technology

• A 14 nm manufacturing process
• SoC architecture
• 3D tri-gate transistors
• Consumer chips up to quad-cores
• Supports SSE4.2 instruction set
• Supports Intel AESNI and PCLMUL instructions
• Supports Intel RDRAND and RDSEED instructions
• Supports Intel SHA extensions
• Supports Intel MPX
• Supports Intel SGX
• 4 MB L2 cache, up from 2MB in Goldmont
• Updated Gen 9 Intel HD Graphics with DirectX 12, OpenGL 4.6, OpenGL ES 3.2 and OpenCL 2.0 support.
• HEVC Main10 & VP9 10-bit Profile2 hardware decoding support
• Integrated native HDMI 2.0 display controller
• 10 W thermal design power desktop processors
• 4.8 to 6.0 W TDP mobile processors
• eMMC 5.1 technology to connect to NAND flash storage
• USB 3.1 & USB-C specification
• Support for DDR4 and LPDDR4 memory
• Supports CNVi

  List of Goldmont Plus processors

Desktop processors (Gemini Lake)

Mobile processors (Gemini Lake)

Desktop processors (Gemini Lake Refresh)

Mobile processors (Gemini Lake Refresh)