Launch Vehicle Digital Computer


The Launch Vehicle Digital Computer was a computer that provided the autopilot for the Saturn V rocket from launch to Earth orbit insertion. Designed and manufactured by IBM's Electronics Systems Center in Owego, N.Y., it was one of the major components of the Instrument Unit, fitted to the S-IVB stage of the Saturn V and Saturn IB rockets. The LVDC also supported pre- and post-launch checkout of the Saturn hardware. It was used in conjunction with the Launch Vehicle Data Adaptor which performed signal conditioning to the sensor inputs to the computer from the launch vehicle.

Hardware

The LVDC was capable of executing 12190 instructions per second. For comparison, a 2012-era microprocessor can execute 4 instructions per cycle at 3 GHz, achieving 12 billion instructions per second, one million times faster.
Its master clock ran at 2.048 MHz, but operations were performed bit-serially, with 4 cycles required to process each bit, 14 bits per phase, and 3 phases per instruction, for a basic time of 168 cycles = 82 μs for a simple add.
Memory was in the form of 13-bit syllables, each with a 14th parity bit. Instructions were one syllable in size, while data words were two syllables. Main memory was random access magnetic core, in the form of 4,096-word memory modules. Up to 8 modules provided a maximum of 32,768 words of memory. Ultrasonic delay lines provided temporary storage.
For reliability, the LVDC used triple-redundant logic and a voting system. The computer included three identical logic systems. Each logic system was split into a seven-stage pipeline. At each stage in the pipeline, a voting system would take a majority vote on the results, with the most popular result being passed on to the next stage in all pipelines. This meant that, for each of the seven stages, one module in any one of the three pipelines could fail, and the LVDC would still produce the correct results.
The result was an estimated reliability of 99.6% over 250 hours of operation, which was far more than the few hours required for an Apollo mission.
With four memory modules, giving a total capacity of 16,384 words, the computer weighed, was in size and consumed

Software architecture and algorithms

LVDC instruction words were split into a 4-bit opcode field and a 9-bit operand address field. This left it with sixteen possible opcode values when there were eighteen different instructions: consequently, three of the instructions used the same opcode value, and used two bits of the address value to determine which instruction was executed.
Memory was broken into 256-word "sectors". 8 bits of the address specified a word within a sector, and the 9th bit selected between the software-selectable "current sector" or a global sector called "residual memory".
The eighteen possible LVDC instructions were:
InstructionOpcodeFunction
HOP0000Transfer execution to a different part of the program. Unlike a modern 'jump' instruction the operand address did not actually specify the address to jump to, but pointed to a 26-bit 'HOP constant' which specified the address.
MPY0001Multiply the contents of the memory location specified in the operand address by the contents of the accumulator register. This instruction took four instruction cycles to complete, but didn't stall program execution, so other instructions could execute before it finished. The result was left in a known register.
SUB0010Subtract the contents of the memory location specified in the operand address from the accumulator register.
DIV0011Divide the contents of the memory location specified in the operand address into the accumulator. This instruction took eight instruction cycles to complete, but didn't stall program execution.
TNZ0100Transfers instruction execution to the operand address specified if the accumulator contents are not zero.
MPH0101Multiply the contents of the memory location specified in the operand address by the contents of the accumulator register. Unlike MPY, this instruction does halt execution until the multiplication is complete.
AND0110Logically AND the contents of the accumulator with the contents of the memory location specified in the operand address.
ADD0111Add the contents of the memory location specified in the operand address to the accumulator register.
TRA1000Transfer execution to the memory location specified in the operand address. The address is within the current instruction sector; the 9th bit of the operand selects the syllable.
XOR1001Logically XOR the contents of the accumulator with the contents of the memory location specified in the operand address.
PIO1010Process input or output: communicate with external hardware via the Data Adapter. "The low order address bits, A1 and A2, determine whether the operation is an input or output instruction. The high order address bits, A8 and A9, determine whether the data contents are transferred from the main memory, residual memory or accumulator."
STO1011Store the contents of the accumulator register in the memory location specified in the operand address.
TMI1100Transfer execution to the operand address specified if the accumulator contents are negative.
RSU1101Contents of the accumulator are subtracted from the contents of the memory location specified in the operand address, and the result left in the accumulator.
SHR01 1110Contents of accumulator are shifted by up to two bits, based on a value in the operand address. This instruction can also clear the accumulator if the operand address bits are zero.
CDSx0 1110Change data sector.
EXM11 1110Transfer execution to one of eight addresses dependent on the operand address, which also specifies modifications to the operand address of the next instruction before it is executed.
CLA1111 load memory.

Programs and algorithms

In flight the LVDC ran a major computation loop every 2 seconds for vehicle guidance, and a minor loop 25 times a second for attitude control. The minor loop is triggered by a dedicated interrupt every 40 ms and takes 18 ms to run.
Unlike the Apollo Guidance Computer software, the software which ran on the LVDC seems to have vanished. While the hardware would be fairly simple to emulate, the only remaining copies of the software are probably in the core memory of the Instrument Unit LVDCs of the remaining Saturn V rockets on display at NASA sites.

Interrupts

The LVDC could also respond to a number of interrupts triggered by external events.
For a Saturn IB these interrupts were:
LVDC Data Word BitFunction
1Internal to LVDC
2Spare
3Simultaneous Memory Error
4Command Decoder Interrupt
5Guidance Reference Release
6Manual Initiation of S-IVB Engine Cutoff
7S-IB Outboard Engines Cutoff
8S-IVB Engine Out
9RCA-110A Interrupt
10S-IB Low Fuel Level Sensors Dry
11RCA-110A Interrupt

For a Saturn V these interrupts were:
LVDC Data Word BitFunction
1Minor Loop Interrupt
2Switch Selector Interrupt
3Computer Interface Unit Interrupt
4Temporary Loss Of Control
5Command Receiver Interrupt
6Guidance Reference Release
7S-II Propellant Depletion/Engine Cutoff
8S-IC Propellant Depletion/Engine Cutoff
9S-IVB Engine Out
10Program Recycle
11S-IC Inboard Engine Out
12Command LVDA/RCA-110A Interrupt

Construction

The LVDC was approximately wide, high, and deep and weighed. The chassis was made of magnesium-lithium alloy LA 141, chosen for its high stiffness, low weight, and good vibration damping characteristics. The chassis was divided into a 3 x 5 matrix of cells separated by walls through which coolant was circulated to remove the of power dissipated by the computer. Slots in the cell walls held "pages" of electronics. The decision to cool the LVDC by circulating coolant through the walls of the computer was unique at the time and allowed the LVDC and LVDA to be placed in one cold plate location due to the three dimensional packaging. The cold plates used to cool most equipment in the Instrument Unit were inefficient from a space view although versatile for the variety of equipment used. The alloy LA 141 had been used by IBM on the Gemini keyboard, read out units, and computer in small quantities and the larger frame of the LVDC was produced from the largest billets of LA 141 cast at the time and subsequently CNC machined into the frame.
A page consisted of two boards back to back and a magnesium-lithium frame to conduct heat to the chassis. The 12-layer boards contained signal, power, and ground layers and connections between layers were made by plated-through holes.
Up to 35 alumina squares of could be reflow soldered to a board. These alumina squares had conductors silk screened to the top side and resistors silk-screened to the bottom side. Semiconductor chips of, each containing either one transistor or two diodes, were reflow soldered to the top side. The complete module was called a unit logic device. The unit logic device was a smaller version of IBM's Solid Logic Technology module, but with clip connections. Copper balls were used for contacts between the chips and the conductive patterns.
The hierarchy of the electronic structure is shown in the following table.
LEVELCOMPONENTMATERIALIBM TERM
1Transistor, diode silicon-
2Up to 14 transistors, diodes and resistors aluminaULD
3Up to 35 ULDs printed circuit boardMIB
4Two MIBsMagnesium-lithium framePage

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