Verilog-AMS


Verilog-AMS is a derivative of the Verilog hardware description language that includes analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which solves the differential equations in analog-domain. Both domains are coupled: analog events can trigger digital actions and vice versa.

Overview

The Verilog-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.
Verilog-AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits. It is particularly well suited for verification of very complex analog, mixed-signal and RF integrated circuits.
Verilog and Verilog/AMS are not procedural programming languages, but event-based hardware description languages. As such, they provide sophisticated and powerful language features for definition and synchronization of parallel actions and events. On the other hand, many actions defined in HDL program statements can run in parallel. However, Verilog/AMS can be coupled with procedural languages like the ANSI C language using the Verilog Procedural Interface of the simulator, which eases testsuite implementation, and allows interaction with legacy code or testbench equipment.
The original intention of the Verilog-AMS committee was a single language for both analog and digital design, however due to delays in the merger process it remains at Accellera while Verilog evolved into SystemVerilog and went to the IEEE.

Code example

Verilog/AMS is a superset of the Verilog digital HDL, so all statements in digital domain work as in Verilog. All analog parts work as in Verilog-A.
The following code example in Verilog-AMS shows a DAC which is an example for analog processing which is triggered by a digital signal:

`include "constants.vams"
`include "disciplines.vams"
// Simple DAC model
module dac_simple;
// Parameters
parameter integer bits = 4 from ;
parameter integer td = 1n from din;
output aout;

//Define port types
logic clk;
logic din;
electrical aout, vref;
// Internal variables
real aout_new, ref;
integer i;
// Change signal in the analog part
analog begin
@ begin // Change output only for rising clock edge

aout_new = 0;
ref = V;

for begin
ref = ref/2;
aout_new = aout_new + ref * din;
end
end
V <+ transition; // Get a smoother transition when output level changes
end
endmodule

The ADC model is reading analog signals in the digital blocks:

`include "constants.vams"
`include "disciplines.vams"
// Simple ADC model
module adc_simple;
// Parameters
parameter integer bits = 4 from; // Number of bits
parameter integer td = 1 from dout;
//Define port types
electrical vref, vin;
logic clk;
reg dout;
// Internal variables
real ref, sample;
integer i;
initial begin
dout = 0;
end
// Perform sampling in the digital blocks for rising clock edge
always @ begin

sample = V;
ref = V;

for begin

ref = ref/2;

if begin
dout <= # 1;
sample = sample - ref;
end
else
dout <= # 0;
end
end
endmodule

General