I3C (bus)


I3C is a specification to enable communication between computer chips by defining the electrical connection between the chips and signaling patterns to be used. The standard defines the electrical connection between the chips to be a two wire, shared, serial data bus, one wire being used as a clock to define the sampling times, the other wire being used as a data line whose voltage can be sampled. The standard defines a signalling protocol in which multiple chips can control communication and thereby act as the bus master.
The I3C specification takes its name from, uses the same electrical connections as, and allows some backward compatibility with, the I²C bus, a de facto standard for inter-chip communication, widely used for low-speed peripherals and sensors in computer systems. The I3C standard is designed to retain some backward compatibility with the I²C system, notably allowing designs where existing I²C devices can be connected to an I3C bus but still have the bus able to switch to a higher data rate for communication at higher speeds between compliant I3C devices. The I3C standard thereby combines the advantage of the simple, two wire I²C architecture with the higher communication speeds common to more complicated buses such as the Serial Peripheral Interface.
The I3C standard was developed as a collaborative effort between electronics and computer related companies under auspices of the Mobile Industry Processor Interface Alliance. The I3C standard was first released to the public at the end of 2017, although access requires the disclosure of private information. Google and Intel have backed I3C as a sensor interface standard for Internet of things devices.

History

Goals of the MIPI Sensor Working Group effort were first announced in November 2014 at the MEMS Executive Congress in Scottsdale AZ.
Electronic design automation tool vendors including Cadence, Synopsys and Silvaco have released controller IP blocks and associated verification software for the implementation of the I3C bus in new integrated circuit designs.
In December 2016, Lattice Semiconductor has integrated I3C support into its new FPGA known as an iCE40 UltraPlus.
In 2017, Qualcomm announced the Snapdragon 845 mobile SOC with integrated I3C master support.
In December 2017, The I3C 1.0 specification was released for public review.
At about the same time, a Linux kernel patch introducing support for I3C was proposed by Boris Brezillon.
In June 2020, Renesas Electronics introduced I3C products.

Goals

Prior to public release of the specification, a substantial amount of general information about it has been published in the form of slides from the 2016 MIPI DevCon. The goals for this interface were based on a survey of MIPI member organizations and MEMS Industry Group members. The results of this survey have been made public.

I3C V1.0

The initial I3C design sought to improve over I2C in the following ways:
After publishing making the I3C 1.0 standard publicly accessible, the organization subsequently published the I3C Basic specification, a subset intended to be implementable by non-member organizations under a RAND-Z licence. The basic version includes many of the protocol innovations in I3C 1.0, but lacks some of the potentially more difficult-to-implement ones such as the optional high data rate modes like DDR. None the less the default SDR mode at up to 12.5 Mbit/s is a major speed/capacity improvement over I2C.

I3C V1.1

Published in December of 2019, this specification is only available to MIPI member.

Nomenclature

Signal Pins

I3C uses two signal pins on referred to as SCL and SDA. In legacy and SDR modes, these signals are used in a way very similarly to I2C:
All communications in I2C and I3C requires framing for synchronization. Within a frame, changes on the SDA line should always occur while SCL is in the low state, so that SDA can be considered stable on the low-to-high transition of SCL. Violations of this general rule are used for framing.
Between data frames, the bus master holds SCL high, in effect stopping the clock, and SDA drivers are in a high-impedance state, permitting a pull-up resistor to float it to high. A high-to-low transition of SDA, while SCL his high, is known as a START symbol, and signals the beginning a new data frame. A low-to-high transition on SDA, while SCL is high, is the STOP symbol, ending a data frame.
In I2C, the START symbol is usually generated by a bus master, but in I3C, even slave devices can pull SDA low to indicate they want to start a frame. This is used to implement some advanced I3C features, such as in-band interrupts, and hot-joins. After the start, the bus master restarts the clock by driving SCL, and begins the bus arbitration process.

Bus Arbitration

At the start of a frame, several devices may contend for use of the bus, and the bus arbitration process serves to select what device to service next. In both I2C and I3C, bus arbitration is done based on the device's address, where devices with the lowest address have higher priority. It is done with the SDA line in open-drain mode, which allows devices transmitting a binary 0 to override devices signaling a binary 1. Contending devices monitor the SDA line while driving it in open-drain mode. If they detect a situation where SDA is low at a time their address required it to be high, they know they have lost the bus arbitration, and must cease their contention until the next frame begins.

Device classes

On an I3C bus in its default mode, four different classes of devices can be supported:
I3C Buses always initialize in SDR mode. To enter HDR mode, the I3C master issues an "Enter HDR" CCC Broadcast command which tells all I3C slaves that
the bus is in HDR mode. I3C slaves which do not support HDR have told that to the master and can ignore that command.
I3C slaves which do not support HDR need to have an "HDR exit" detector which informs when it is time to listen to the bus again.
HDR modes operate in either Double Data Rate or Ternary Symbol modes. These modes can only be on buses under one of two limited configurations:
There are three possible HDR modes: