List of 7400-series integrated circuits
The following is a list of 7400-series digital logic integrated circuits. The original 7400-series integrated circuits were made by Texas Instruments with the prefix "SN" to create the name SN74xx. Due to the popularity of these parts, other manufacturers released pin-to-pin compatible logic devices which kept the 7400 sequence number as an aid to identification of compatible parts. However, different manufacturers use different prefixes or no prefix at all.
Overview
Some TTL logic parts were made with an extended military-specification temperature range. These parts are prefixed with 54 instead of 74 in the part number.A short-lived 64 prefix on Texas Instruments parts indicated an industrial temperature range; this prefix had been dropped from the TI literature by 1973. Most recent 7400 series parts are fabricated in CMOS or BiCMOS technology rather than TTL. Surface mount parts with a single gate are prefixed with 741G instead of 74.
Some manufacturers released some 4000-series equivalent CMOS circuits with a 74 prefix, for example the 74HC4066 was a replacement for the 4066 with slightly different electrical characteristics. See List of 4000-series integrated circuits.
Conversely, the 4000-series has "borrowed" from the 7400 series - such as the CD40193 and CD40161 being pin-for-pin functional replacements for 74C193 and 74C161.
Older TTL parts made by manufacturers such as Signetics, Motorola, Mullard and Siemens may have different numeric prefix and numbering series entirely, such as in the European FJ family FJH101 is an 8-input NAND gate like a 7430.
A few alphabetic characters to designate a specific logic subfamily may immediately follow the 74 or 54 in the
part number, e.g., 74LS74 for Low-power Schottky. Some CMOS parts such as 74HCT74 for High-speed CMOS with TTL-compatible input thresholds are functionally similar to the TTL part. Not all functions are available in all families.
The generic descriptive feature of these alphabetic characters was diluted by various companies participating in the market at its peak, and are not always consistent especially with more recent offerings. The National Semiconductor trademarks of the words FAST and FACT
are usually cited in the descriptions from other companies when describing their own unique designations.
In a few instances, such as the 7478 and 74107, the same suffix in different families do not have completely equivalent logic functions.
Another extension to the series is the 7416xxx variant, representing mostly the 16-bit wide counterpart of otherwise 8-bit-wide "base" chips with the same three ending digits. Thus e.g. a "7416373" would be the 16-bit-wide equivalent of a "74373". Some 7416xxx parts, however, do not have a direct counterpart from the standard 74xxx range but deliver new functionality instead, which needs making use of the 7416xxx series' higher pin count. For more details, refer primarily to the Texas Instruments documentation mentioned in the References section.
For CMOS subfamilies, read "open drain" for "open collector" in the table below.
There are a few numeric suffixes that have multiple conflicting assignments, such as the 74453.
Larger footprints
Parts in this section have a pin count of 14 pins or more. The lower part numbers were established in the 1960s and 1970s, then higher part numbers were added incrementally over decades. IC manufacturers continue to make a core subset of this group, but many of these part numbers are considered obsolete and no longer manufactured. Older discontinued parts may be available from a limited number of sellers as new old stock, though some are much harder to find.For the following table:
- Part number column - the "x" is a place holder for the logic subfamily name. For example, 74x00 in "LS" logic family would be "74LS00".
- Description column - the terms Schmitt-trigger, open-collector/open-drain, three-state were moved to the input and output columns to make it easier to sort by those features.
- Input column - a blank cell means a normal input for the logic family type.
- Output column - a blank cell means a 'totem pole' output, also known as a push–pull output, with the ability to drive ten standard inputs of the same logic subfamily. Outputs with higher output currents are often called drivers or buffers.
- Pins column - number of pins for the dual in-line package version; a number in brackets indicates that there is no known dual in-line package version of this IC.
Units | Description | Input | Output | Pins | Datasheet | |
74x00 | 4 | quad 2-input NAND gate | 14 | |||
74x01 | 4 | quad 2-input NAND gate | open-collector | 14 | ||
74x02 | 4 | quad 2-input NOR gate | 14 | |||
74x03 | 4 | quad 2-input NAND gate | open-collector | 14 | ||
74x04 | 6 | hex inverter gate | 14 | |||
74x05 | 6 | hex inverter gate | open-collector | 14 | ||
74x06 | 6 | hex inverter gate | open-collector 30 V / 40 mA | 14 | ||
74x07 | 6 | hex buffer gate | open-collector 30 V / 40 mA | 14 | ||
74x08 | 4 | quad 2-input AND gate | 14 | |||
74x09 | 4 | quad 2-input AND gate | open-collector | 14 | ||
74x10 | 3 | triple 3-input NAND gate | 14 | |||
74x11 | 3 | triple 3-input AND gate | 14 | |||
74x12 | 3 | triple 3-input NAND gate | open-collector | 14 | ||
74x13 | 2 | dual 4-input NAND gate | Schmitt-trigger | 14 | ||
74x14 | 6 | hex inverter gate | Schmitt-trigger | 14 | ||
74x15 | 3 | triple 3-input AND gate | open-collector | 14 | ||
74x16 | 6 | hex inverter gate | open-collector 15 V / 40 mA | 14 | ||
74x17 | 6 | hex buffer gate | open-collector 15 V / 40 mA | 14 | ||
74x18 | 2 | dual 4-input NAND gate | Schmitt-trigger | 14 | ||
74x19 | 6 | hex inverter gate | Schmitt-trigger | 14 | ||
74x20 | 2 | dual 4-input NAND gate | 14 | |||
74x21 | 2 | dual 4-input AND gate | 14 | |||
74x22 | 2 | dual 4-input NAND gate | open-collector | 14 | ||
74x23 | 2 | dual 4-input NOR gate with strobe, one gate expandable with 74x60 | 16 | |||
74x24 | 4 | quad 2-input NAND gate | Schmitt-trigger | 14 | ||
74x25 | 2 | dual 4-input NOR gate with strobe | 14 | |||
74x26 | 4 | quad 2-input NAND gate | open-collector 15 V | 14 | ||
74x27 | 3 | triple 3-input NOR gate | 14 | |||
74x28 | 4 | quad 2-input NOR gate | driver NO=30 | 14 | ||
74x29 | 2 | dual 4-input NOR gate | 14 | |||
74x30 | 1 | single 8-input NAND gate | 14 | |||
74x31 | 6 | hex delay elements | 16 | |||
74x32 | 4 | quad 2-input OR gate | 14 | |||
74x33 | 4 | quad 2-input NOR gate | open-collector driver NO=30 | 14 | ||
74x34 | 6 | hex buffer gate | 14 | |||
74x35 | 6 | hex buffer gate | open-collector | 14 | ||
74x36 | 4 | quad 2-input NOR gate | 14 | |||
74x37 | 4 | quad 2-input NAND gate | driver NO=30 | 14 | ||
74x38 | 4 | quad 2-input NAND gate | open-collector driver NO=30 | 14 | ||
74x39 | 4 | quad 2-input NAND gate | open-collector 60 mA | 14 | ||
74x40 | 2 | dual 4-input NAND gate | driver NO=30 | 14 | ||
74x41 | 1 | BCD to decimal decoder / Nixie tube driver | open-collector 70 V | 16 | ||
74x42 | 1 | BCD to decimal decoder | 16 | |||
74x43 | 1 | excess-3 to decimal decoder | 16 | |||
74x44 | 1 | Gray code to decimal decoder | 16 | |||
74x45 | 1 | BCD to decimal decoder/driver | open-collector 30 V / 80 mA | 16 | ||
74x46 | 1 | BCD to 7-segment display decoder/driver | open-collector 30 V | 16 | ||
74x47 | 1 | BCD to 7-segment decoder/driver | open-collector 15 V | 16 | ||
74x48 | 1 | BCD to 7-segment decoder/driver | open-collector, 2 kΩ pull-up | 16 | ||
74x49 | 1 | BCD to 7-segment decoder/driver | open-collector | 14 | ||
74x50 | 2 | dual 2-2-input AND-OR-Invert gate, one gate expandable | 14 | |||
7451, 74H51, 74S51 | 2 | dual 2-2-input AND-OR-Invert gate | 14 | |||
74L51, 74LS51 | 2 | 3-3-input AND-OR-Invert gate and 2-2-input AND-OR-Invert gate | 14 | |||
74x52 | 1 | 3-2-2-2-input AND-OR gate, expandable with 74x61 | 14 | |||
7453 | 1 | 2-2-2-2-input AND-OR-Invert gate, expandable | 14 | |||
74H53 | 1 | 3-2-2-2-input AND-OR-Invert gate, expandable | 14 | |||
7454 | 1 | 2-2-2-2-input AND-OR-Invert gate | 14 | |||
74H54 | 1 | 3-2-2-2-input AND-OR-Invert gate | 14 | |||
74L54, 74LS54 | 1 | 3-3-2-2-input AND-OR-Invert gate | 14 | |||
74x55 | 1 | 4-4-input AND-OR-Invert gate, 74H55 is expandable | 14 | |||
74x56 | 1 | 50:1 frequency divider | 8 | |||
74x57 | 1 | 60:1 frequency divider | 8 | |||
74x58 | 2 | 3-3-input AND-OR gate and 2-2-input AND-OR gate | 14 | |||
74x59 | 2 | dual 3-2-input AND-OR-Invert gate | 14 | |||
74x60 | 2 | dual 4-input expander for 74x23, 74x50, 74x53, 74x55 | 14 | |||
74x61 | 3 | triple 3-input expander for 74x52 | 14 | |||
74x62 | 1 | 3-3-2-2-input AND-OR expander for 74x50, 74x53, 74x55 | 14 | |||
74x63 | 6 | hex current sensing interface gates | 14 | |||
74x64 | 1 | 4-3-2-2-input AND-OR-Invert gate | 14 | |||
74x65 | 1 | 4-3-2-2 input AND-OR-Invert gate | open-collector | 14 | ||
74x67 | 1 | AND gated J-K master-slave flip-flop, asynchronous preset and clear | ||||
74L68 | 2 | dual J-K flip-flop, asynchronous clear | ||||
74LS68 | 2 | dual 4-bit decade counters | 16 | |||
74L69 | 2 | dual J-K flip-flop, asynchronous preset, common clock and clear | ||||
74LS69 | 2 | dual 4-bit binary counters | 16 | |||
74x70 | 1 | AND-gated positive edge triggered J-K flip-flop, asynchronous preset and clear | 14 | |||
74H71 | 1 | AND-OR-gated J-K master-slave flip-flop, preset | 14 | |||
74L71 | 1 | AND-gated R-S master-slave flip-flop, preset and clear | 14 | |||
74x72 | 1 | AND gated J-K master-slave flip-flop, asynchronous preset and clear | 14 | |||
74x73 | 2 | dual J-K flip-flop, asynchronous clear | 14 | |||
74x74 | 2 | dual D positive edge triggered flip-flop, asynchronous preset and clear | 14 | |||
74x75 | 2 | 4-bit bistable latch, complementary outputs | 16 | |||
74x76 | 2 | dual J-K flip-flop, asynchronous preset and clear | 16 | |||
74x77 | 1 | 4-bit bistable latch | 14 | |||
74H78 | 2 | dual positive pulse triggered J-K flip-flop, preset, common clock and common clear | 14 | |||
74L78 | 2 | dual positive pulse triggered J-K flip-flop, preset, common clock and common clear | 14 | |||
74LS78 | 2 | dual negative edge triggered J-K flip-flop, preset, common clock and common clear | 14 | |||
74x79 | 2 | dual D positive edge triggered flip-flop, asynchronous preset and clear | 14 | |||
74x80 | 1 | gated full adder | 14 | |||
74x81 | 1 | 16-bit RAM | 14 | |||
74x82 | 1 | 2-bit binary full adder | 14 | |||
74x83 | 1 | 4-bit binary full adder | 16 | |||
74x84 | 1 | 16-bit RAM | 16 | |||
74x85 | 1 | 4-bit magnitude comparator | 16 | |||
74x86 | 4 | quad 2-input XOR gate | 14 | |||
74x87 | 1 | 4-bit true/complement/zero/one element | 14 | |||
74x88 | 1 | 256-bit ROM | open-collector | 16 | ||
74x89 | 1 | 64-bit RAM, inverted outputs | open-collector | 16 | ||
74x90 | 1 | decade counter | 14 | |||
74x91 | 1 | 8-bit shift register, serial in, serial out, gated input | 14 | |||
74x92 | 1 | divide-by-12 counter | 14 | |||
74x93 | 1 | 4-bit binary counter | 14 | |||
74x94 | 1 | 4-bit shift register, dual asynchronous presets | 16 | |||
74x95 | 1 | 4-bit shift register, parallel in, parallel out, serial input | 14 | |||
74x96 | 1 | 5-bit parallel-in/parallel-out shift register, asynchronous preset | 16 | |||
74x97 | 1 | synchronous 6-bit binary rate multiplier | 16 | |||
74x98 | 1 | 4-bit data selector/storage register | 16 | |||
74x99 | 1 | 4-bit bidirectional universal shift register | 16 | |||
Units | Description | Input | Output | Pins | Datasheet | |
74x100 | 2 | dual 4-bit bistable latch | 24 | |||
74x101 | 1 | AND-OR-gated J-K negative-edge-triggered flip-flop, preset | 14 | |||
74x102 | 1 | AND-gated J-K negative-edge-triggered flip-flop, preset and clear | 14 | |||
74x103 | 2 | dual J-K negative-edge-triggered flip-flop, clear | 14 | |||
74x104 | 1 | J-K master-slave flip-flop | 14 | |||
74x105 | 1 | J-K master-slave flip-flop, J2 and K2 inverted | 14 | |||
74x106 | 2 | dual J-K negative-edge-triggered flip-flop, preset and clear | 16 | |||
74x107 | 2 | dual J-K flip-flop, clear | 14 | |||
74x107A | 2 | dual J-K negative-edge-triggered flip-flop, clear | 14 | |||
74x108 | 2 | dual J-K negative-edge-triggered flip-flop, preset, common clear and common clock | 14 | |||
74x109 | 2 | dual J-Not-K positive-edge-triggered flip-flop, clear and preset | 16 | |||
74x110 | 1 | AND-gated J-K master-slave flip-flop, data lockout | 14 | |||
74x111 | 2 | dual J-K master-slave flip-flop, data lockout, reset, set | 16 | |||
74x112 | 2 | dual J-K negative-edge-triggered flip-flop, clear and preset | 16 | |||
74x113 | 2 | dual J-K negative-edge-triggered flip-flop, preset | 14 | |||
74x114 | 2 | dual J-K negative-edge-triggered flip-flop, preset, common clock and clear | 14 | |||
74x115 | 2 | dual J-K master-slave flip-flop, data lockout, reset | 14 | |||
74116 | 2 | dual 4-bit latch, clear | 24 | |||
74H116 | 1 | AND-gated J-K flip flop | 14 | |||
74x117 | 1 | AND-gated J-K flip flop, one J and K input inverted | 14 | |||
74x118 | 6 | hex set/reset latch, common reset | 16 | |||
74119 | 6 | hex set/reset latch | 24 | |||
74H119 | 2 | dual J-K flip-flop, shared clear and clock inputs | 14 | |||
74120 | 2 | dual pulse synchronizer/drivers | 15 kΩ pull-up | 16 | ||
74H120 | 2 | dual J-K flip-flop, separate clock inputs | 14 | |||
74x121 | 1 | monostable multivibrator | Schmitt-trigger | 14 | ||
74x122 | 1 | retriggerable monostable multivibrator, clear | 14 | |||
74x123 | 2 | dual retriggerable monostable multivibrator, clear | 16 | |||
74x124 | 2 | dual voltage-controlled oscillator | analog | 16 | ||
74x125 | 4 | quad bus buffer, negative enable | three-state | 14 | ||
74x126 | 4 | quad bus buffer, positive enable | three-state | 14 | ||
74x128 | 4 | quad 2-input NOR gate | driver 50 Ω | 14 | ||
74x130 | 2 | retriggerable monostable multivibrator | 16 | |||
74x131 | 4 | quad 2-input AND gate | open-collector 15 V | 14 | ||
74x132 | 4 | quad 2-input NAND gate | Schmitt-trigger | 14 | ||
74x133 | 1 | single 13-input NAND gate | 16 | |||
74x134 | 1 | single 12-input NAND gate | three-state | 16 | ||
74x135 | 4 | quad XOR/XNOR gate, two inputs to select logic type | 16 | |||
74x136 | 4 | quad 2-input XOR gate | open-collector | 14 | ||
74x137 | 1 | 3-line to 8-line decoder/demultiplexer, address latch, inverting outputs | 16 | |||
74x138 | 1 | 3-line to 8-line decoder/demultiplexer, inverting outputs | 16 | |||
74x139 | 2 | dual 2 to 4-line decoder/demultiplexer, inverting outputs | 16 | |||
74x140 | 2 | dual 4-input NAND | driver 50 Ω | 14 | ||
74x141 | 1 | BCD to decimal decoder/driver for cold-cathode indicator / Nixie tube | open-collector 60 V | 16 | ||
74x142 | 1 | decade counter/latch/decoder/driver for Nixie tubes | open-collector 60 V | 16 | ||
74x143 | 1 | decade counter/latch/decoder/7-segment driver | constant current 15 mA | 24 | ||
74x144 | 1 | decade counter/latch/decoder/7-segment driver | open-collector 15 V / 25 mA | 24 | ||
74x145 | 1 | BCD to decimal decoder/driver | open-collector 15 V / 80 mA | 16 | ||
74x146 | 1 | 3-line to 8-line decoder | ||||
74x147 | 1 | 10-line to 4-line priority encoder | 16 | |||
74x148 | 1 | 8-line to 3-line priority encoder | 16 | |||
74x149 | 1 | 8-line to 8-line priority encoder | 20 | |||
74x150 | 1 | 16-line to 1-line data selector/multiplexer | 24 | |||
74x151 | 1 | 8-line to 1-line data selector/multiplexer | 16 | |||
74x152 | 1 | 8-line to 1-line data selector/multiplexer, inverting output | 14 | |||
74x153 | 2 | dual 4-line to 1-line data selector/multiplexer, non-inverting outputs | 16 | |||
74x154 | 1 | 4-line to 16-line decoder/demultiplexer, inverting outputs | 24 | |||
74x155 | 2 | dual 2-line to 4-line decoder/demultiplexer, inverting outputs | 16 | |||
74x156 | 2 | dual 2-line to 4-line decoder/demultiplexer, inverting outputs | open-collector | 16 | ||
74x157 | 4 | quad 2-line to 1-line data selector/multiplexer, non-inverting outputs | 16 | |||
74x158 | 4 | quad 2-line to 1-line data selector/multiplexer, inverting outputs | 16 | |||
74x159 | 1 | 4-line to 16-line decoder/demultiplexer | open-collector | 24 | ||
74x160 | 1 | synchronous presettable 4-bit decade counter, asynchronous clear | 16 | |||
74x161 | 1 | synchronous presettable 4-bit binary counter, asynchronous clear | 16 | |||
74x162 | 1 | synchronous presettable 4-bit decade counter, synchronous clear | 16 | |||
74x163 | 1 | synchronous presettable 4-bit binary counter, synchronous clear | 16 | |||
74x164 | 1 | 8-bit serial-in parallel-out shift register, asynchronous clear, not output latch | 14 | |||
74x165 | 1 | 8-bit parallel-in serial-out shift register, parallel load, complementary outputs | 16 | |||
74x166 | 1 | parallel-load 8-bit shift register | 16 | |||
74x167 | 1 | synchronous decade rate multiplier | 16 | |||
74x168 | 1 | synchronous presettable 4-bit up/down decade counter | 16 | |||
74x169 | 1 | synchronous presettable 4-bit up/down binary counter | 16 | |||
74x170 | 1 | 16-bit register file | open-collector | 16 | ||
74x171 | 4 | quad D flip-flops, clear | 16 | |||
74x172 | 1 | 16-bit multiple port register file | three-state | 24 | ||
74x173 | 4 | quad D flip-flop, asynchronous clear | three-state | 16 | ||
74x174 | 6 | hex D flip-flop, common asynchronous clear | 16 | |||
74x175 | 4 | quad D edge-triggered flip-flop, complementary outputs and asynchronous clear | 16 | |||
74x176 | 1 | presettable decade counter/latch | 14 | |||
74x177 | 1 | presettable binary counter/latch | 14 | |||
74x178 | 1 | 4-bit parallel-access shift register | 14 | |||
74x179 | 1 | 4-bit parallel-access shift register, asynchronous clear input, complementary Qd output | 16 | |||
74x180 | 1 | 9-bit odd/even parity bit generator and checker | 14 | |||
74x181 | 1 | 4-bit arithmetic logic unit and function generator | 24 | |||
74x182 | 1 | lookahead carry generator | 16 | |||
74x183 | 2 | dual carry-save full adder | 14 | |||
74x184 | 1 | BCD to binary converter | open-collector | 16 | ||
74x185 | 1 | 6-bit binary to BCD converter | open-collector | 16 | ||
74x186 | 1 | 512-bit ROM | open-collector | 24 | ||
74x187 | 1 | 1024-bit ROM | open-collector | 16 | ||
74x188 | 1 | 256-bit PROM | open-collector | 16 | ||
74x189 | 1 | 64-bit RAM, inverting outputs | three-state | 16 | ||
74x190 | 1 | synchronous presettable up/down 4-bit decade counter | 16 | |||
74x191 | 1 | synchronous presettable up/down 4-bit binary counter | 16 | |||
74x192 | 1 | synchronous presettable up/down 4-bit decade counter, clear | 16 | |||
74x193 | 1 | synchronous presettable up/down 4-bit binary counter, clear | 16 | |||
74x194 | 1 | 4-bit bidirectional universal shift register | 16 | |||
74x195 | 1 | 4-bit parallel-access shift register | 16 | |||
74x196 | 1 | presettable 4-bit decade counter/latch | 14 | |||
74x197 | 1 | presettable 4-bit binary counter/latch | 14 | |||
74x198 | 1 | 8-bit bidirectional universal shift register | 24 | |||
74x199 | 1 | 8-bit universal shift register, J-Not-K serial inputs | 24 | |||
Units | Description | Input | Output | Pins | Datasheet | |
74x200 | 1 | 256-bit RAM | three-state | 16 | ||
74x201 | 1 | 256-bit RAM | three-state | 16 | ||
74x202 | 1 | 256-bit RAM with power down | three-state | 16 | ||
74x206 | 1 | 256-bit RAM | open-collector | 16 | ||
74x207 | 1 | 1024-bit RAM | three-state | 16 | ||
74x208 | 1 | 1024-bit RAM, separate data in- and outputs | three-state | 20 | ||
74x209 | 1 | 1024-bit RAM | three-state | 16 | ||
74x210 | 8 | octal buffer, inverting | three-state | 20 | ||
74x211 | 1 | 144-bit RAM with output latch | three-state | 20 | ||
74x212 | 1 | 144-bit RAM | three-state | 20 | ||
74x213 | 1 | 192-bit RAM | three-state | 20 | ||
74x214 | 1 | 1024-bit RAM | three-state | 16 | ||
74x215 | 1 | 1024-bit RAM with power-down mode | three-state | 16 | ||
74x216 | 1 | 256-bit RAM, common I/O | three-state | 16 | ||
74x217 | 1 | 256-bit RAM | three-state | 20 | ||
74x218 | 1 | 256-bit RAM | three-state | 20 | ||
74x219 | 1 | 64-bit RAM, non-inverting outputs | three-state | 16 | ||
74x221 | 2 | dual monostable multivibrator | Schmitt-trigger | 16 | ||
74x222 | 1 | 64-bit FIFO memory, synchronous, input/output ready enable | three-state | 20 | ||
74x224 | 1 | 64-bit FIFO memory, synchronous | three-state | 16 | ||
74x225 | 1 | 80-bit FIFO memory, asynchronous | three-state | 20 | ||
74x226 | 1 | 4-bit parallel latched bus transceiver | three-state | 16 | ||
74x227 | 1 | 64-bit FIFO memory, synchronous, input/output ready enable | open-collector | 20 | ||
74x228 | 1 | 64-bit FIFO memory, synchronous | open-collector | 20 | ||
74x229 | 1 | 80-bit FIFO memory, asynchronous | three-state | 20 | ||
74x230 | 2 | dual 4-bit buffer/driver, one inverted, one non-inverted; negative enable | three-state | 20 | ||
74x231 | 2 | dual 4-bit buffer/driver, both inverted; one positive and one negative enable | three-state | 20 | ||
74x232 | 1 | 64-bit FIFO memory, asynchronous | three-state | 16 | ||
74x233 | 1 | 80-bit FIFO memory, asynchronous | three-state | 20 | ||
74x234 | 1 | 256-bit FIFO memory, asynchronous | three-state | 16 | ||
74x235 | 1 | 320-bit FIFO memory, asynchronous | three-state | 20 | ||
74x236 | 1 | 256-bit FIFO memory, asynchronous | three-state | 16 | ||
74x237 | 1 | 3-of-8 decoder/demultiplexer, address latch, active high outputs | 16 | |||
74x238 | 1 | 3-of-8 decoder/demultiplexer, active high outputs | 16 | |||
74x239 | 2 | dual 2-of-4 decoder/demultiplexer, active high outputs | 16 | |||
74x240 | 8 | octal buffer, inverting outputs | Schmitt-trigger | three-state | 20 | |
74x241 | 8 | octal buffer, non-inverting outputs | Schmitt-trigger | three-state | 20 | |
74x242 | 4 | quad bus transceiver, inverting outputs | Schmitt-trigger | three-state | 14 | |
74x243 | 4 | quad bus transceiver, non-inverting outputs | Schmitt-trigger | three-state | 14 | |
74x244 | 8 | octal buffer, non-inverting outputs | Schmitt-trigger | three-state | 20 | |
74x245 | 8 | octal bus transceiver, non-inverting outputs | Schmitt-trigger | three-state | 20 | |
74x246 | 1 | BCD to 7-segment decoder/driver | open-collector 30 V | 16 | ||
74x247 | 1 | BCD to 7-segment decoder/driver | open-collector 15 V | 16 | ||
74x248 | 1 | BCD to 7-segment decoder/driver | open-collector, 2 kΩ pull-up | 16 | ||
74x249 | 1 | BCD to 7-segment decoder/driver | open-collector | 16 | ||
74x250 | 1 | 1 of 16 data selector/multiplexer | three-state | 24 | ||
74x251 | 1 | 8-line to 1-line data selector/multiplexer, complementary outputs | three-state | 16 | ||
74x253 | 2 | dual 4-line to 1-line data selector/multiplexer | three-state | 16 | ||
74x255 | 2 | dual 2-line to 4-line decoder/demultiplexer, inverting outputs | three-state | 16 | ||
74x256 | 2 | dual 4-bit addressable latch | 16 | |||
74x257 | 4 | quad 2-line to 1-line data selector/multiplexer, non-inverting outputs | three-state | 16 | ||
74x258 | 4 | quad 2-line to 1-line data selector/multiplexer, inverting outputs | three-state | 16 | ||
74x259 | 1 | 8-bit addressable latch | 16 | |||
74x260 | 2 | dual 5-input NOR gate | 14 | |||
74x261 | 1 | 2-bit by 4-bit parallel binary multiplier | 16 | |||
74x262 | 1 | 5760-bit ROM | three-state | 20 | ||
74x264 | 1 | look ahead carry generator | 16 | |||
74x265 | 4 | quad complementary output elements | 16 | |||
74x266 | 4 | quad 2-input XNOR gate | open-collector | 14 | ||
74x268 | 6 | hex D-type latches, common output control, common enable | three-state | 16 | ||
74x269 | 1 | 8-bit bidirectional binary counter | 24 | |||
74x270 | 1 | 2048-bit ROM | open-collector | 16 | ||
74x271 | 1 | 2048-bit ROM | open-collector | 20 | ||
74x273 | 1 | 8-bit register, asynchronous clear | 20 | |||
74x274 | 1 | 4-bit by 4-bit binary multiplier | three-state | 20 | ||
74x275 | 1 | 7-bit slice Wallace tree | three-state | 16 | ||
74x276 | 4 | quad J-Not-K edge-triggered flip-flops, separate clocks, common preset and clear | 20 | |||
74x278 | 1 | 4-bit cascadeable priority registers, latched data inputs | 14 | |||
74x279 | 4 | quad set-reset latch | 16 | |||
74x280 | 1 | 9-bit odd/even parity bit generator/checker | 14 | |||
74x281 | 1 | 4-bit parallel binary accumulator | 24 | |||
74x282 | 1 | look-ahead carry generator, selectable carry inputs | 20 | |||
74x283 | 1 | 4-bit binary full adder | 16 | |||
74x284 | 1 | 4-bit by 4-bit parallel binary multiplier | 16 | |||
74x285 | 1 | 4-bit by 4-bit parallel binary multiplier | 16 | |||
74x286 | 1 | 9-bit parity generator/checker, bus driver parity I/O port | 14 | |||
74x287 | 1 | 1024-bit PROM | three-state | 16 | ||
74x288 | 1 | 256-bit PROM | three-state | 16 | ||
74x289 | 1 | 64-bit RAM, inverted outputs | open-collector | 16 | ||
74x290 | 1 | decade counter | 14 | |||
74x292 | 1 | programmable frequency divider/digital timer | 16 | |||
74x293 | 1 | 4-bit binary counter | 14 | |||
74x294 | 1 | programmable frequency divider/digital timer | 16 | |||
74x295 | 1 | 4-bit bidirectional shift register | three-state | 14 | ||
74x297 | 1 | digital phase-locked loop filter | 16 | |||
74x298 | 4 | quad 2-input multiplexer, storage | 16 | |||
74x299 | 1 | 8-bit bidirectional universal shift/storage register | three-state | 20 | ||
Units | Description | Input | Output | Pins | Datasheet | |
74x300 | 1 | 256-bit RAM | open-collector | 16 | ||
74x301 | 1 | 256-bit RAM | open-collector | 16 | ||
74x302 | 1 | 256-bit RAM | open-collector | 16 | ||
74x303 | 1 | octal divide-by-2 clock driver, 2 outputs inverted | 16 | |||
74x304 | 1 | octal divide-by-2 clock driver | 16 | |||
74x305 | 1 | octal divide-by-2 clock driver, 4 outputs inverted | 16 | |||
74x309 | 1 | 1024-bit RAM | open-collector | 16 | ||
74x310 | 8 | octal buffer, inverting | Schmitt-trigger | three-state | 20 | |
74x311 | 1 | 144-bit RAM with output latch | open-collector | 20 | ||
74x312 | 1 | 144-bit RAM | open-collector | 20 | ||
74x313 | 1 | 192-bit RAM | open-collector | 20 | ||
74x314 | 1 | 1024-bit RAM | open-collector | 16 | ||
74x315 | 1 | 1024-bit RAM with power-down mode | open-collector | 16 | ||
74x316 | 1 | 256-bit RAM, common I/O | open-collector | 16 | ||
74x317 | 1 | 256-bit RAM | open-collector | 20 | ||
74x318 | 1 | 256-bit RAM | open-collector | 20 | ||
74x319 | 1 | 64-bit RAM | open-collector | 16 | ||
74x320 | 1 | crystal-controlled oscillator | 16 | |||
74x321 | 1 | crystal-controlled oscillators, F/2 and F/4 count-down outputs | 16 | |||
74x322 | 1 | 8-bit shift register, sign extend | three-state | 20 | ||
74x323 | 1 | 8-bit bidirectional universal shift/storage register, synchronous clear | three-state | 20 | ||
74x324 | 1 | voltage-controlled oscillator, enable input, complementary outputs | analog | 14 | ||
74x325 | 2 | dual voltage-controlled oscillator, complementary outputs | analog | 16 | ||
74x326 | 2 | dual voltage-controlled oscillator, enable input, complementary outputs | analog | 16 | ||
74x327 | 2 | dual voltage-controlled oscillator | analog | 14 | ||
74x330 | 1 | PLA | three-state | 20 | ||
74x331 | 1 | PLA | open-collector, 2.5 kΩ pull-up | 20 | ||
74x333 | 1 | PLA | three-state | 24 | ||
74x334 | 1 | PLA | three-state | 24 | ||
74x335 | 1 | PLA | open-collector | 24 | ||
74x336 | 1 | PLA | open-collector | 24 | ||
74x337 | 1 | clock driver | three-state | 20 | ||
74x340 | 8 | octal buffer, inverting outputs | Schmitt-trigger | three-state | 20 | |
74x341 | 8 | octal buffer, non-inverting outputs | Schmitt-trigger | three-state | 20 | |
74x344 | 8 | octal buffer, non-inverting outputs | Schmitt-trigger | three-state | 20 | |
74x347 | 1 | BCD-to-7 segment decoders/drivers, low voltage version of 7447 | open-collector | 16 | ||
74x348 | 1 | 8 to 3-line priority encoder | three-state | 16 | ||
74x350 | 1 | 4-bit shifter | three-state | 16 | ||
74x351 | 2 | dual 8-line to 1-line data selectors/multiplexers, 4 common data inputs | three-state | 20 | ||
74x352 | 2 | dual 4-line to 1-line data selectors/multiplexers, inverting outputs | 16 | |||
74x353 | 2 | dual 4-line to 1-line data selectors/multiplexers, inverting outputs | three-state | 16 | ||
74x354 | 1 | 8-line to 1-line data selector/multiplexer, transparent registers | three-state | 20 | ||
74x355 | 1 | 8-line to 1-line data selector/multiplexer, transparent registers | open-collector | 20 | ||
74x356 | 1 | 8-line to 1-line data selector/multiplexer, edge-triggered registers | three-state | 20 | ||
74x357 | 1 | 8-line to 1-line data selector/multiplexer, edge-triggered registers | open-collector | 20 | ||
74x361 | 1 | bubble memory function timing generator | 22 | |||
74x362 | 1 | four-phase clock generator/driver for Texas Instruments TMS9900 | 20 | |||
74x363 | 1 | octal transparent latch | three-state | 20 | ||
74x364 | 1 | octal edge-triggered D-type register | three-state | 20 | ||
74x365 | 6 | hex buffer, non-inverting outputs | three-state | 16 | ||
74x366 | 6 | hex buffer, inverting outputs | three-state | 16 | ||
74x367 | 6 | hex buffer, non-inverting outputs | three-state | 16 | ||
74x368 | 6 | hex buffer, inverting outputs | three-state | 16 | ||
74x370 | 1 | 2048-bit ROM | three-state | 16 | ||
74x371 | 1 | 2048-bit ROM | three-state | 20 | ||
74x373 | 8 | octal transparent latch | three-state | 20 | ||
74x374 | 8 | octal register | three-state | 20 | ||
74x375 | 4 | quad bistable latch | 16 | |||
74x376 | 4 | quad J-Not-K flip-flop, common clock and common clear | 16 | |||
74x377 | 1 | 8-bit register, clock enable | 20 | |||
74x378 | 1 | 6-bit register, clock enable | 16 | |||
74x379 | 1 | 4-bit register, clock enable and complementary outputs | 16 | |||
74x380 | 1 | 8-bit multifunction register | three-state | 24 | ||
74x381 | 1 | 4-bit arithmetic logic unit/function generator, generate and propagate outputs | 20 | |||
74x382 | 1 | 4-bit arithmetic logic unit/function generator, ripple carry and overflow outputs | 20 | |||
74x383 | 1 | 8-bit register | open-collector | 20 | ||
74x384 | 1 | 8-bit by 1-bit two's complement multipliers | 16 | |||
74x385 | 4 | quad serial adder/subtractor | 20 | |||
74x386 | 4 | quad 2-input XOR gate | 14 | |||
74x387 | 1 | 1024-bit PROM | open-collector | 16 | ||
74x388 | 1 | 4-bit D-type register | three-state and standard | 16 | ||
74x390 | 2 | dual 4-bit decade counter | 16 | |||
74x393 | 2 | dual 4-bit binary counter | 14 | |||
74x395 | 1 | 4-bit cascadable shift register | three-state | 16 | ||
74x396 | 8 | octal storage registers, parallel access | 16 | |||
74x398 | 4 | quad 2-input multiplexers, storage and complementary outputs | 20 | |||
74x399 | 4 | quad 2-input multiplexer, storage | 16 | |||
Units | Description | Input | Output | Pins | Datasheet | |
74x401 | 1 | CRC generator/checker | 14 | |||
74x402 | 1 | serial data polynomial generator/checker | 16 | |||
74x403 | 1 | 64-bit FIFO memory | three-state | 24 | ||
74x405 | 1 | 3-line to 8-line decoder | 16 | |||
74x406 | 1 | 3-line to 8-line decoder | 14 | |||
74x407 | 1 | data access register | three-state | 24 | ||
74408 | 1 | 8-bit parity tree | 14 | |||
74S408 | 1 | controller/driver for 16k/64k/256k dRAM | 48 | |||
74x409 | 1 | controller/driver for 16k/64k/256k dRAM | 48 | |||
74x410 | 1 | 64-bit RAM with output register | three-state | 18 | ||
74x411 | 1 | FIFO RAM controller | 40 | |||
74x412 | 1 | multi-mode buffered 8-bit latches | three-state | 24 | ||
74x413 | 1 | 256-bit FIFO memory | 16 | |||
74x414 | 1 | interrupt priority controller for Intel 8080 | 24 | |||
74416 | 1 | modulo 10 counter, preload and clear inputs | 16 | |||
74S416 | 1 | 4-bit bidirectional bus transceiver, non-inverting | three-state | 16 | ||
74x417 | 2 | modulo 2 and modulo 5 counters, common preload and clear inputs | 16 | |||
74418 | 1 | modulo 16 counter, preload and clear inputs | 16 | |||
74F418 | 1 | 32-bit error detection and correction circuit | three-state | 48 | ||
74419 | 2 | dual modulo 4 counters, common preload and clear inputs | 16 | |||
74S419 | 1 | FIFO RAM controller | 40 | |||
74x420 | 1 | 32-bit check bit / syndrome bit generator | three-state | 48 | ||
74x422 | 1 | retriggerable monostable multivibrators, two inputs | 14 | |||
74x423 | 2 | dual retriggerable monostable multivibrator | 16 | |||
74x424 | 1 | two-phase clock generator/driver for Intel 8080 | 16 | |||
74x425 | 4 | quad bus buffers, active low enables | three-state | 14 | ||
74x426 | 4 | quad bus buffers, active high enables | three-state | 14 | ||
74x428 | 1 | system controller for Intel 8080A | 28 | |||
74x429 | 1 | FIFO RAM controller | three-state | 28 | ||
74x430 | 1 | cyclic redundancy checker/corrector | 28 | |||
74x432 | 1 | 8-bit multi-mode buffered latch | three-state | 24 | ||
74x433 | 1 | 256-bit FIFO memory | three-state | 24 | ||
74x436 | 1 | line driver/memory driver circuits - MOS memory interface, damping output resistor | 16 | |||
74x437 | 1 | line driver/memory driver circuits - MOS memory interface | 16 | |||
74x438 | 1 | system controller for Intel 8080A | 28 | |||
74x440 | 4 | quad tridirectional bus transceiver, non-inverting outputs | open-collector | 20 | ||
74x441 | 4 | quad tridirectional bus transceiver, inverting outputs | open-collector | 20 | ||
74x442 | 4 | quad tridirectional bus transceiver, non-inverting outputs | three-state | 20 | ||
74x443 | 4 | quad tridirectional bus transceiver, inverting outputs | three-state | 20 | ||
74x444 | 4 | quad tridirectional bus transceiver, inverting and non-inverting outputs | three-state | 20 | ||
74x445 | 1 | BCD-to-decimal decoders/drivers | driver 80 mA | 16 | ||
74x446 | 4 | quad bus transceivers, direction controls, inverting outputs | three-state | 16 | ||
74x447 | 1 | BCD-to-7-segment decoders/drivers, low voltage version of 74247 | open-collector | 16 | ||
74x448 | 4 | quad tridirectional bus transceiver, inverting and non-inverting outputs | open-collector | 20 | ||
74x449 | 4 | quad bus transceivers, direction controls, non-inverting outputs | three-state | 16 | ||
74450 | 1 | counter, latch, 7-segment decoder | open-collector | 16 | ||
74S450 | 1 | 8192-bit PROM with power-down | three-state | 24 | ||
74LS450 | 1 | 16-to-1 multiplexer, complementary outputs | 24 | |||
74S451 | 1 | 8192-bit PROM with power-down | open-collector | 24 | ||
74LS451 | 2 | dual 8-to-1 multiplexer | 24 | |||
74x452 | 2 | dual decade counter, synchronous | 16 | |||
74453 | 2 | dual binary counter, synchronous | 16 | |||
74LS453 | 4 | quad 4-to-1 multiplexer | 24 | |||
74x454 | 2 | dual decade up/down counter, synchronous, preset input | 24 | |||
74455 | 2 | dual binary up/down counter, synchronous, preset input | 24 | |||
74F455 | 1 | octal buffer / line driver with parity, inverting | three-state | 24 | ||
74456 | 1 | 4-bit NBCD full adder | 16 | |||
74F456 | 1 | octal buffer / line driver with parity, non-inverting | three-state | 24 | ||
74x458 | 1 | nines complement / zero element | 14 | |||
74460 | 1 | 4-bit bus transfer switch | three-state | 16 | ||
74LS460 | 1 | 10-bit comparator | 24 | |||
74x461 | 1 | 8-bit presettable binary counter | three-state | 24 | ||
74x462 | 1 | fiber-optic data-link transmitter | open-collector 100 mA and standard | 20 | ||
74x463 | 1 | fiber-optic data-link receiver | analog | 20 | ||
74x465 | 8 | octal buffer, non-inverting outputs | three-state | 20 | ||
74x466 | 8 | octal buffers, inverting outputs | three-state | 20 | ||
74x467 | 8 | octal buffers, non-inverting outputs | three-state | 20 | ||
74x468 | 8 | octal buffers, inverting outputs | three-state | 20 | ||
74x469 | 1 | 8-bit synchronous up/down counter, parallel load and hold capability | three-state | 24 | ||
74x470 | 1 | 2048-bit PROM | open-collector | 20 | ||
74x471 | 1 | 2048-bit PROM | three-state | 20 | ||
74x472 | 1 | 4096-bit PROM | three-state | 20 | ||
74x473 | 1 | 4096-bit PROM | open-collector | 20 | ||
74x474 | 1 | 4096-bit PROM | three-state | 24 | ||
74x475 | 1 | 4096-bit PROM | open-collector | 24 | ||
74x476 | 1 | 4096-bit PROM | three-state | 18 | ||
74x477 | 1 | 4096-bit PROM | open-collector | 18 | ||
74x478 | 1 | 8192-bit PROM | three-state | 24 | ||
74x479 | 1 | 8192-bit PROM | open-collector | 24 | ||
74x480 | 1 | single burst error recovery circuit | 24 | |||
74x481 | 1 | 4-bit slice cascadable processor elements | ||||
74x482 | 1 | 4-bit slice expandable control elements | 20 | |||
74x484 | 1 | BCD-to-binary converter | three-state | 20 | ||
74x485 | 1 | binary-to-BCD converter | three-state | 20 | ||
74x488 | 1 | IEEE-488 bus interface | 48 | |||
74x490 | 2 | dual decade counter | 16 | |||
74x491 | 1 | 10-bit binary up/down counter, limited preset | three-state | 24 | ||
74x498 | 1 | 8-bit bidirectional shift register, parallel inputs | three-state | 24 | ||
Units | Description | Input | Output | Pins | Datasheet | |
74x500 | 1 | 6-bit flash analog-to-digital converter | analog | 24 | ||
74x502 | 1 | 8-bit successive approximation register | 16 | |||
74x503 | 1 | 8-bit successive approximation register with expansion control | 16 | |||
74x504 | 1 | 12-bit successive approximation register with expansion control | 24 | |||
74x505 | 1 | 8-bit successive approximation ADC | analog | three-state | 24 | |
74x508 | 1 | 8-bit multiplier/divider | 24 | |||
74x516 | 1 | 16-bit multiplier/divider | 24 | |||
74x518 | 1 | 8-bit comparator | 20 kΩ pull-up | open-collector | 20 | |
74x519 | 1 | 8-bit comparator | open-collector | 20 | ||
74x520 | 1 | 8-bit comparator, inverting output | 20 kΩ pull-up | 20 | ||
74x521 | 1 | 8-bit comparator, inverting output | 20 | |||
74x522 | 1 | 8-bit comparator, inverting output | 20 kΩ pull-up | open-collector | 20 | |
74x524 | 1 | 8-bit registered comparator | open-collector | 20 | ||
74x525 | 1 | 16-bit programmable counter | 28 | |||
74x526 | 1 | fuse programmable identity comparator, 16-bit | 20 | |||
74x527 | 1 | fuse programmable identity comparator, 8-bit + 4-bit conventional Identity comparator | 20 | |||
74x528 | 1 | fuse programmable Identity comparator, 12-bit | 16 | |||
74x531 | 8 | octal transparent latch | three-state | 20 | ||
74x532 | 8 | octal register | three-state | 20 | ||
74x533 | 1 | octal transparent latch, inverting outputs | three-state | 20 | ||
74x534 | 1 | octal register, inverting outputs | three-state | 20 | ||
74x535 | 1 | octal transparent latch, inverting outputs | three-state | 20 | ||
74x536 | 1 | octal register, inverting outputs | three-state | 20 | ||
74x537 | 1 | BCD to decimal decoder | three-state | 20 | ||
74x538 | 1 | 3-line to 8-line decoder/demultiplexer | three-state | 20 | ||
74x539 | 2 | dual 2-line to 4-line decoder/demultiplexer | three-state | 20 | ||
74x540 | 1 | inverting octal buffer | Schmitt-trigger | three-state | 20 | |
74x541 | 1 | non-inverting octal buffer | Schmitt-trigger | three-state | 20 | |
74x543 | 1 | octal registered transceiver, non-inverting | three-state | 24 | ||
74x544 | 1 | octal registered transceiver, inverting | three-state | 24 | ||
74x545 | 1 | octal bidirectional transceiver, non-inverting | three-state | 20 | ||
74x546 | 1 | 8-bit bidirectional registered transceiver, non-inverting | three-state | 24 | ||
74LS547 | 1 | 8-bit bidirectional latched transceiver, non-inverting | three-state | 24 | ||
74F547 | 1 | 3-line to 8-line decoder/demultiplexer with address latches and acknowledge output | 20 | |||
74LS548 | 1 | 8-bit two-stage pipelined register | three-state | 24 | ||
74F548 | 1 | 3-line to 8-line decoder/demultiplexer with acknowledge output | 20 | |||
74x549 | 1 | 8-bit two-stage pipelined latch | three-state | 24 | ||
74x550 | 1 | octal registered transceiver with status flags, non-inverting | three-state | 28 | ||
74x551 | 1 | octal registered transceiver with status flags, inverting | three-state | 28 | ||
74x552 | 1 | octal registered transceiver with parity and flags | three-state | 28 | ||
74x556 | 1 | 16x16-bit multiplier slice | three-state | |||
74x557 | 1 | 8-bit by 8-bit multiplier | three-state | 40 | ||
74x558 | 1 | 8-bit by 8-bit multiplier | three-state | 40 | ||
74x559 | 1 | 8-bit expandable two's complement multiplier/divider | three-state | 24 | ||
74x560 | 1 | 4-bit decade counter | three-state | 20 | ||
74x561 | 1 | 4-bit binary counter | three-state | 20 | ||
74x563 | 1 | 8-bit D-type transparent latch, inverting outputs | three-state | 20 | ||
74x564 | 1 | 8-bit D-type edge-triggered register, inverting outputs | three-state | 20 | ||
74x566 | 1 | 8-bit bidirectional registered transceiver, inverting | three-state | 24 | ||
74x567 | 1 | 8-bit bidirectional latched transceiver, inverting | three-state | 24 | ||
74x568 | 1 | decade up/down counter | three-state | 20 | ||
74x569 | 1 | binary up/down counter | three-state | 20 | ||
74x570 | 1 | 2048-bit PROM | open-collector | 16 | ||
74x571 | 1 | 2048-bit PROM | three-state | 16 | ||
74x572 | 1 | 4096-bit PROM | open-collector | 18 | ||
74x573 | 1 | octal D-type transparent latch | three-state | 20 | ||
74x574 | 1 | octal D-type edge-triggered flip-flop | three-state | 20 | ||
74x575 | 1 | octal D-type edge-triggered flip-flop, synchronous clear | three-state | 24 | ||
74x576 | 1 | octal D-type edge-triggered flip-flop, inverting outputs | three-state | 20 | ||
74x577 | 1 | octal D-type edge-triggered flip-flop, synchronous clear, inverting outputs | three-state | 24 | ||
74x579 | 1 | 8-bit bidirectional binary counter | three-state | 20 | ||
74x580 | 1 | octal D-type transparent latch, inverting outputs | three-state | 20 | ||
74x582 | 1 | 4-bit BCD arithmetic logic unit | 24 | |||
74x583 | 1 | 4-bit BCD adder | 16 | |||
74x588 | 1 | octal bidirectional transceiver with IEEE-488 termination resistors | three-state | 20 | ||
74x589 | 1 | 8-bit shift register, input latch | three-state | 16 | ||
74x590 | 1 | 8-bit binary counter, output registers | three-state | 16 | ||
74x591 | 1 | 8-bit binary counter, output registers | open-collector | 16 | ||
74x592 | 1 | 8-bit binary counter, input registers | 16 | |||
74x593 | 1 | 8-bit binary counter, input registers | three-state | 20 | ||
74x594 | 1 | 8-bit shift registers, Serial-In, Parallel-Out, output latches | buffered | 16 | ||
74x595 | 1 | 8-bit shift registers, Serial-In, Parallel-Out, output latches, output enable | three-state | 16 | ||
74x596 | 1 | 8-bit shift registers, Serial-In, Parallel-Out, output latches, output enable | open-collector | 16 | ||
74x597 | 1 | 8-bit shift registers, Parallel-In, Serial-Out, input latches | 16 | |||
74x598 | 1 | 8-bit shift register, Selectable Parallel-In/Out input latches | three-state | 20 | ||
74x599 | 1 | 8-bit shift registers, Serial-In, Parallel-Out, output latches | open-collector | 16 | ||
Units | Description | Input | Output | Pins | Datasheet | |
74x600 | 1 | dynamic memory refresh controller, transparent and burst modes, for 4K or 16K dRAM | three-state | 20 | ||
74x601 | 1 | dynamic memory refresh controller, transparent and burst modes, for 64K dRAM | three-state | 20 | ||
74x602 | 1 | dynamic memory refresh controller, cycle steal and burst modes, for 4K or 16K dRAM | three-state | 20 | ||
74x603 | 1 | dynamic memory refresh controller, cycle steal and burst modes, for 64K dRAM | three-state | 20 | ||
74x604 | 1 | octal 2-input multiplexer, latch, high-speed | three-state | 28 | ||
74x605 | 1 | octal 2-input multiplexer, latch, high-speed | open-collector | 28 | ||
74x606 | 1 | octal 2-input multiplexer, latch, glitch-free | three-state | 28 | ||
74x607 | 1 | octal 2-input multiplexer, latch, glitch-free | open-collector | 28 | ||
74x608 | 1 | memory cycle controller | 16 | |||
74x610 | 1 | memory mapper, latched | three-state | 40 | ||
74x611 | 1 | memory mapper, latched | open-collector | 40 | ||
74x612 | 1 | memory mapper | three-state | 40 | ||
74x613 | 1 | memory mapper | open-collector | 40 | ||
74x614 | 1 | octal bus transceiver and register, inverting | open-collector | 24 | ||
74x615 | 1 | octal bus transceiver and register, non-inverting | open-collector | 24 | ||
74x616 | 1 | 16-bit parallel error detection and correction | three-state | 40 | ||
74x617 | 1 | 16-bit parallel error detection and correction | open-collector | 40 | ||
74x620 | 1 | octal bus transceiver, inverting | three-state | 20 | ||
74x621 | 1 | octal bus transceiver, non-inverting | open-collector | 20 | ||
74x622 | 1 | octal bus transceiver, inverting | open-collector | 20 | ||
74x623 | 1 | octal bus transceiver, non-inverting | three-state | 20 | ||
74x624 | 1 | voltage-controlled oscillator, enable control, range control, two-phase outputs | analog | 14 | ||
74x625 | 2 | dual voltage-controlled oscillator, two-phase outputs | analog | 16 | ||
74x626 | 2 | dual voltage-controlled oscillator, enable control, two-phase outputs | analog | 16 | ||
74x627 | 2 | dual voltage-controlled oscillator | analog | 14 | ||
74x628 | 1 | voltage-controlled oscillator, enable control, range control, external temperature compensation, two-phase outputs | analog | 14 | ||
74x629 | 2 | dual voltage-controlled oscillator, enable control, range control | analog | 16 | ||
74x630 | 1 | 16-bit error detection and correction | three-state | 28 | ||
74x631 | 1 | 16-bit error detection and correction | open-collector | 28 | ||
74x632 | 1 | 32-bit parallel error detection and correction, byte-write | three-state | 52 | ||
74x633 | 1 | 32-bit parallel error detection and correction, byte-write | open-collector | 52 | ||
74x634 | 1 | 32-bit parallel error detection and correction | three-state | 48 | ||
74x635 | 1 | 32-bit parallel error detection and correction | open-collector | 48 | ||
74x636 | 1 | 8-bit parallel error detection and correction | three-state | 20 | ||
74x637 | 1 | 8-bit parallel error detection and correction | open-collector | 20 | ||
74x638 | 1 | octal bus transceiver, inverting outputs | three-state and open-collector | 20 | ||
74x639 | 1 | octal bus transceiver, non-inverting outputs | three-state and open-collector | 20 | ||
74x640 | 1 | octal bus transceiver, inverting outputs | three-state | 20 | ||
74x641 | 1 | octal bus transceiver, non-inverting outputs | open-collector | 20 | ||
74x642 | 1 | octal bus transceiver, inverting outputs | open-collector | 20 | ||
74x643 | 1 | octal bus transceiver, mix of inverting and non-inverting outputs | three-state | 20 | ||
74x644 | 1 | octal bus transceiver, mix of inverting and non-inverting outputs | open-collector | 20 | ||
74x645 | 1 | octal bus transceiver, non-inverting outputs | three-state | 20 | ||
74x646 | 1 | octal bus transceiver/latch/multiplexer, non-inverting outputs | three-state | 24 | ||
74x647 | 1 | octal bus transceiver/latch/multiplexer, non-inverting outputs | open-collector | 24 | ||
74x648 | 1 | octal bus transceiver/latch/multiplexer, inverting outputs | three-state | 24 | ||
74x649 | 1 | octal bus transceiver/latch/multiplexer, inverting outputs | open-collector | 24 | ||
74x651 | 1 | octal bus transceiver/register, inverting outputs | three-state | 24 | ||
74x652 | 1 | octal bus transceiver/register, non-inverting outputs | three-state | 24 | ||
74x653 | 1 | octal bus transceiver/register, inverting outputs | three-state and open-collector | 24 | ||
74x654 | 1 | octal bus transceiver/register, non-inverting outputs | three-state and open-collector | 24 | ||
74x655 | 1 | octal buffer / line driver with parity, inverting | three-state | 24 | ||
74x656 | 1 | octal buffer / line driver with parity, non-inverting | three-state | 24 | ||
74x657 | 1 | octal bidirectional transceiver with 8-bit parity generator/checker | three-state | 24 | ||
74x658 | 1 | octal bus transceiver, parity, inverting | three-state | 24 | ||
74x659 | 1 | octal bus transceiver, parity, non-inverting | three-state | 24 | ||
74x664 | 1 | octal bus transceiver, parity, inverting | three-state | 24 | ||
74x665 | 1 | octal bus transceiver, parity, non-inverting | three-state | 24 | ||
74x666 | 1 | 8-bit D-type transparent read-back latch, non-inverting | three-state | 24 | ||
74x667 | 1 | 8-bit D-type transparent read-back latch, inverting | three-state | 24 | ||
74x668 | 1 | synchronous 4-bit decade up/down counter | 16 | |||
74x669 | 1 | synchronous 4-bit binary up/down counter | 16 | |||
74x670 | 1 | 16-bit register file | three-state | 16 | ||
74x671 | 1 | 4-bit bidirectional shift register/latch/multiplexer, direct clear | three-state | 20 | ||
74x672 | 1 | 4-bit bidirectional shift register/latch/multiplexer, synchronous clear | three-state | 20 | ||
74x673 | 1 | 16-bit serial-in, serial/parallel-out shift register, output storage registers | three-state | 24 | ||
74x674 | 1 | 16-bit parallel-in, serial-out shift register | three-state | 24 | ||
74x675 | 1 | 16-bit serial-in, serial/parallel-out shift register | 24 | |||
74x676 | 1 | 16-bit serial/parallel-in, serial-out shift register | 24 | |||
74x677 | 1 | 16-bit address comparator, enable | 24 | |||
74x678 | 1 | 16-bit address comparator, latch | 24 | |||
74x679 | 1 | 12-bit address comparator, latch | 20 | |||
74x680 | 1 | 12-bit address comparator, enable | 20 | |||
74x681 | 1 | 4-bit parallel binary accumulator | three-state | 20 | ||
74x682 | 1 | 8-bit magnitude comparator, P>Q output | 20 kΩ pull-up | 20 | ||
74x683 | 1 | 8-bit magnitude comparator, P>Q output | 20 kΩ pull-up | open-collector | 20 | |
74x684 | 1 | 8-bit magnitude comparator, P>Q output | 20 | |||
74x685 | 1 | 8-bit magnitude comparator, P>Q output | open-collector | 20 | ||
74x686 | 1 | 8-bit magnitude comparator, P>Q output, enable | 24 | |||
74x687 | 1 | 8-bit magnitude comparator, P>Q output, enable | open-collector | 24 | ||
74x688 | 1 | 8-bit magnitude comparator, enable | 20 | |||
74x689 | 1 | 8-bit magnitude comparator, enable | open-collector | 20 | ||
74x690 | 1 | 4-bit decimal counter/latch/multiplexer, asynchronous clear | three-state | 20 | ||
74x691 | 1 | 4-bit binary counter/latch/multiplexer, asynchronous clear | three-state | 20 | ||
74x692 | 1 | 4-bit decimal counter/latch/multiplexer, synchronous clear | three-state | 20 | ||
74x693 | 1 | 4-bit binary counter/latch/multiplexer, synchronous clear | three-state | 20 | ||
74x694 | 1 | 4-bit decimal counter/latch/multiplexer, synchronous and asynchronous clears | three-state | 20 | ||
74x695 | 1 | 4-bit binary counter/latch/multiplexer, synchronous and asynchronous clears | three-state | 20 | ||
74x696 | 1 | 4-bit decimal counter/register/multiplexer, asynchronous clear | three-state | 20 | ||
74x697 | 1 | 4-bit binary counter/register/multiplexer, asynchronous clear | three-state | 20 | ||
74x698 | 1 | 4-bit decimal counter/register/multiplexer, synchronous clear | three-state | 20 | ||
74x699 | 1 | 4-bit binary counter/register/multiplexer, synchronous clear | three-state | 20 | ||
Units | Description | Input | Output | Pins | Datasheet | |
74x700 | 1 | octal dRAM driver, inverting | three-state | 20 | ||
74x701 | 1 | 8-bit register/counter/comparator | three-state | 24 | ||
74x702 | 1 | 8-bit registered read-back transceiver | three-state | 24 | ||
74x705 | 1 | arithmetic logic unit for digital signal processing applications | three-state | |||
74x707 | 1 | 8-bit TTL-ECL shift register | 20 | |||
74x708 | 1 | 576-bit FIFO memory | three-state | 28 | ||
74x710 | 1 | 8-bit single-supply TTL-ECL shift register | 20 | |||
74x711 | 5 | quint 2-to-1 multiplexers | three-state | 20 | ||
74x712 | 5 | quint 3-to-1 multiplexers | 24 | |||
74x715 | 1 | programmable video sync generator | 20 | |||
74x716 | 1 | programmable decade counter | 16 | |||
74x718 | 1 | programmable binary counter | 16 | |||
74x723 | 1 | 576-bit FIFO memory | three-state | 28 | ||
74x724 | 1 | voltage-controlled multivibrator | analog | 8 | ||
74x725 | 1 | 4608-bit FIFO memory | three-state | 28 | ||
74x730 | 1 | octal dRAM driver, inverting | three-state | 20 | ||
74x731 | 1 | octal dRAM driver, non-inverting | three-state | 20 | ||
74x732 | 1 | 4-bit 3-bus multiplexer, inverting | three-state | 20 | ||
74x733 | 1 | 4-bit 3-bus multiplexer, non-inverting | three-state | 20 | ||
74x734 | 1 | octal dRAM driver, non-inverting | three-state | 20 | ||
74x740 | 2 | dual 4-bit line driver, inverting | three-state | 20 | ||
74x741 | 2 | dual 4-bit line driver, non-inverting, complementary enable inputs | three-state | 20 | ||
74x744 | 2 | dual 4-bit line driver, non-inverting | three-state | 20 | ||
74x746 | 1 | octal buffer / line driver, inverting | 20 kΩ pull-up | three-state | 20 | |
74x747 | 1 | octal buffer / line driver, non-inverting | 20 kΩ pull-up | three-state | 20 | |
74x748 | 1 | 8 to 3-line priority encoder | 16 | |||
74x756 | 1 | octal buffer/line driver, inverting outputs | open-collector | 20 | ||
74x757 | 1 | octal buffer/line driver, non-inverting outputs, complementary enable inputs | open-collector | 20 | ||
74x758 | 1 | quadruple bus transceivers, inverting outputs | open-collector | 14 | ||
74x759 | 1 | quadruple bus transceivers, non-inverting outputs | open-collector | 14 | ||
74x760 | 1 | octal buffer/line driver, non-inverting outputs | open-collector | 20 | ||
74x762 | 1 | octal buffer/line driver, inverting and non-inverting outputs | open-collector | 20 | ||
74x763 | 1 | octal buffer/line driver, inverting outputs, complementary enable inputs | open-collector | 20 | ||
74x764 | 1 | dual-port dRAM controller | 40 | |||
74x765 | 1 | dual-port dRAM controller with address latch | 40 | |||
74x776 | 1 | 8-bit latched transceiver for FutureBus | three-state and open-collector | 28 | ||
74x779 | 1 | 8-bit bidirectional binary counter | three-state | 16 | ||
74x783 | 1 | synchronous address multiplexer for display systems | 40 | |||
74x784 | 1 | 8-bit serial/parallel multiplier with adder/subtractor | 20 | |||
74x786 | 1 | 4-input asynchronous bus arbiter | 16 | |||
74x790 | 1 | error detection and correction | three-state | 48 | ||
74x793 | 1 | 8-bit latch, readback | 20 | |||
74x794 | 1 | 8-bit register, readback | 20 | |||
74x795 | 1 | octal buffer, non-inverting, common enable | three-state | 20 | ||
74x796 | 1 | octal buffer, inverting, common enable | three-state | 20 | ||
74x797 | 1 | octal buffer, non-inverting, enable for 4 buffers each | three-state | 20 | ||
74x798 | 1 | octal buffer, inverting, enable for 4 buffers each | three-state | 20 | ||
Units | Description | Input | Output | Pins | Datasheet | |
74x800 | 3 | triple 4-input AND/NAND drivers | driver | 20 | ||
74x802 | 3 | triple 4-input OR/NOR drivers | driver | 20 | ||
74x803 | 4 | quad D flip flops with matched propagation delays | 14 | |||
74x804 | 6 | hex 2-input NAND drivers | driver | 20 | ||
74x805 | 6 | hex 2-input NOR drivers | driver | 20 | ||
74x807 | 1 | 1-to-10 clock driver | driver | 20 | ||
74x808 | 6 | hex 2-input AND drivers | driver | 20 | ||
74x810 | 4 | quad 2-input XNOR gates | 14 | |||
74x811 | 4 | quad 2-input XNOR gates | open-collector | 14 | ||
74x818 | 1 | 8-bit diagnostic register | three-state | 24 | ||
74x821 | 1 | 10-bit bus interface flip-flop | three-state | 24 | ||
74x822 | 1 | 10-bit bus interface flip-flop, inverting inputs | three-state | 24 | ||
74x823 | 1 | 9-bit D-type flip-flops, clear and clock enable inputs | three-state | 24 | ||
74x824 | 1 | 9-bit D-type flip-flops, clear and clock enable inputs, inverting inputs | three-state | 24 | ||
74x825 | 1 | 8-bit D-type flip-flop, clear and clock enable inputs | three-state | 24 | ||
74x826 | 1 | 8-bit D-type flip-flop, clear and clock enable inputs, inverting inputs | three-state | 24 | ||
74x827 | 1 | 10-bit buffer, non-inverting | three-state | 24 | ||
74x828 | 1 | 10-bit buffer, inverting | three-state | 24 | ||
74x832 | 6 | hex 2-input OR drivers | driver | 20 | ||
74x833 | 1 | 8-bit to 9-bit bus transceiver with parity register, non-inverting | three-state | 24 | ||
74x834 | 1 | 8-bit to 9-bit bus transceiver with parity register, inverting | three-state | 24 | ||
74x839 | 1 | field-programmable logic array 14x32x6 | three-state | 24 | ||
74x840 | 1 | field-programmable logic array 14x32x6 | open-collector | 24 | ||
74x841 | 1 | 10-bit D-type flip-flop | three-state | 24 | ||
74x842 | 1 | 10-bit D-type flip-flop, inverting inputs | three-state | 24 | ||
74x843 | 1 | 9-bit D flip-flops, clear and set inputs | three-state | 24 | ||
74x844 | 1 | 9-bit D flip-flops, clear and set inputs, inverting inputs | three-state | 24 | ||
74x845 | 1 | 8-bit D flip-flops, clear and set inputs | three-state | 24 | ||
74x846 | 1 | 8-bit D flip-flops, clear and set inputs, inverting inputs | three-state | 24 | ||
74x848 | 1 | 8 to 3-line priority encoder | three-state | 16 | ||
74x850 | 1 | 1 of 16 data selector/multiplexer, clocked select | three-state | 28 | ||
74x851 | 1 | 1 of 16 data selector/multiplexer | three-state | 28 | ||
74x852 | 1 | 8-bit universal transceiver port controller | three-state | 24 | ||
74x853 | 1 | 8-bit to 9-bit bus transceiver with parity latch, non-inverting | three-state | 24 | ||
74x854 | 1 | 8-bit to 9-bit bus transceiver with parity latch, inverting | three-state | 24 | ||
74x856 | 1 | 8-bit universal transceiver port controller | three-state | 24 | ||
74x857 | 6 | hex 2-line to 1-line multiplexer | three-state | 24 | ||
74x861 | 1 | 10-bit bus transceiver, non-inverting | three-state | 24 | ||
74x862 | 1 | 10-bit bus transceiver, inverting | three-state | 24 | ||
74x863 | 1 | 9-bit bus transceiver, non-inverting | three-state | 24 | ||
74x864 | 1 | 9-bit bus transceiver, inverting | three-state | 24 | ||
74x866 | 1 | 8-bit magnitude comparator with latches | 24 | |||
74x867 | 1 | synchronous 8-bit up/down counter, asynchronous clear | 24 | |||
74x869 | 1 | synchronous 8-bit up/down counter, synchronous clear | 24 | |||
74x870 | 1 | dual 16x4 register files | 24 | |||
74x871 | 1 | dual 16x4 register files | 28 | |||
74x873 | 2 | dual 4-bit transparent latch with clear | three-state | 24 | ||
74x874 | 2 | dual 4-bit edge-triggered D flip-flops with clear | three-state | 24 | ||
74x876 | 2 | dual 4-bit edge-triggered D flip-flops with set, inverting outputs | three-state | 24 | ||
74x877 | 1 | 8-bit universal transceiver port controller | three-state | 24 | ||
74x878 | 2 | dual 4-bit D-type flip-flop, synchronous clear, non-inverting outputs | three-state | 24 | ||
74x879 | 2 | dual 4-bit D-type flip-flop, synchronous clear, inverting outputs | three-state | 24 | ||
74x880 | 2 | dual 4-bit transparent latch with clear, inverting outputs | three-state | 24 | ||
74x881 | 1 | 4-bit arithmetic logic unit | 24 | |||
74x882 | 1 | 32-bit lookahead carry generator | 24 | |||
74x885 | 1 | 8-bit magnitude comparator | 24 | |||
74x887 | 1 | 8-bit processor element | ||||
74x888 | 1 | 8-bit processor slice | 64 | |||
74x889 | 1 | 8-bit processor slice | ||||
74x890 | 1 | microoperation sequencer | 64 | |||
74x891 | 1 | microoperation sequencer | ||||
74x895 | 1 | 8-bit memory address generator | ||||
74x897 | 1 | 16-bit parallel/serial barrel shifter | ||||
74x899 | 1 | 9-bit latchable transceiver with parity generator / checker | three-state | |||
Units | Description | Input | Output | Pins | Datasheet | |
74x900 | 4 | quad 2-input NAND gate | driver | 14 | ||
74x901 | 6 | hex inverting TTL buffer | 14 | |||
74C902 | 6 | hex non-inverting TTL buffer | 14 | |||
74ALS902 | 4 | quad 2-input NOR gate | driver | 14 | ||
74C903 | 6 | hex inverting PMOS buffer | 14 | |||
74ALS903 | 4 | quad 2-input NAND gate | open-collector driver | 14 | ||
74x904 | 6 | hex non-inverting PMOS buffer | 14 | |||
74x905 | 1 | 12-bit successive approximation register | 24 | |||
74x906 | 6 | hex open drain n-channel buffers | open-collector | 14 | ||
74x907 | 6 | hex open drain p-channel buffers | 14 | |||
74x908 | 2 | dual 2-input NAND 30 V / 250 mA relay driver | 8 | |||
74x909 | 4 | quad voltage comparator | analog | open-collector | 14 | |
74x910 | 1 | 256-bit RAM | three-state | 18 | ||
74x911 | 1 | 4-digit expandable display controller | three-state | 28 | ||
74x912 | 1 | 6-digit BCD display controller and driver | three-state | 28 | ||
74x913 | 1 | 6-digit BCD display controller and driver, no decimal point | 24 | |||
74x914 | 6 | hex Schmitt trigger, extended input voltage | Schmitt-trigger | 14 | ||
74x915 | 1 | 7-segment to BCD converter | three-state | 18 | ||
74x917 | 1 | 6-digit hex display controller and driver | three-state | 28 | ||
74x918 | 2 | dual 2-input NAND 30 V / 250 mA relay driver | 14 | |||
74x920 | 1 | 1024-bit RAM, separate data inputs and outputs | three-state | 22 | ||
74x921 | 1 | 1024-bit RAM | three-state | 18 | ||
74x922 | 1 | 16-key encoder | three-state | 18 | ||
74x923 | 1 | 20-key encoder | three-state | 20 | ||
74x925 | 1 | 4-digit counter/display driver | 16 | |||
74x926 | 1 | 4-digit decade counter/display driver, carry out and latch | 16 | |||
74x927 | 1 | 4-digit timer counter/display driver | 16 | |||
74x928 | 1 | 4-digit counter/display driver | 16 | |||
74x929 | 1 | 1024-bit RAM, single chip select | three-state | 16 | ||
74x930 | 1 | 1024-bit RAM, three chip selects | three-state | 18 | ||
74x932 | 1 | phase comparator | 8 | |||
74x933 | 1 | 7-bit address bus comparator | 20 | |||
74934 | 1 | =ADC0829 ADC, see corresponding NSC datasheet | ||||
74x935 | 1 | ADC for 3.5-digit digital voltmeters, multiplexed 7-segment display outputs | analog | 28 | ||
74x936 | 1 | ADC for 3.75-digit digital voltmeters, multiplexed 7-segment display outputs | analog | |||
74x937 | 1 | ADC for 3.5-digit digital voltmeters, multiplexed BCD outputs | analog | 24 | ||
74x938 | 1 | ADC for 3.75-digit digital voltmeters, multiplexed BCD outputs | analog | 24 | ||
74x940 | 1 | octal bus/line drivers/line receivers | Schmitt-trigger | three-state | 20 | |
74x941 | 1 | octal bus/line drivers/line receivers | Schmitt-trigger | three-state | 20 | |
74x942 | 1 | 300 baud Bell 103 modem | 20 | |||
74x943 | 1 | 300 baud Bell 103 modem | 20 | |||
74x945 | 1 | 4-digit up/down counter, decoder and LCD driver, output latch | 40 | |||
74x946 | 1 | 4.5-digit counter, decoder and LCD driver, leading zero blanking | 40 | |||
74x947 | 1 | 4-digit up/down counter, decoder and LCD driver, leading zero blanking | 40 | |||
74x948 | 1 | 8-bit ADC with 16-channel analog multiplexer | analog | three-state | 40 | |
74x949 | 1 | 8-bit ADC with 8-channel analog multiplexer | analog | three-state | 28 | |
74x950 | 1 | 8-bit ADC with 8-channel analog multiplexer and sample and hold | analog | three-state | 28 | |
74x952 | 1 | dual rank 8-bit shift register, synchronous clear | three-state | 18 | ||
74C956 | 1 | 4-digit,17-segment alpha-numeric LED display driver with memory and decoder | 40 | |||
74BCT956 | 1 | octal bus transceiver and latch | three-state | 24 | ||
74x962 | 1 | dual rank 8-bit shift register, register exchange mode | three-state | 18 | ||
74x963 | 1 | dual rank 8-bit shift register, synchronous clear | three-state | 20 | ||
74x964 | 1 | dual rank 8-bit shift register, synchronous and asynchronous clear | three-state | 20 | ||
74x968 | 1 | controller/driver for 16k/64k/256k/1M dRAM | 52 | |||
74x978 | 1 | octal flip-flop with serial scanner | 24 | |||
74x979 | 1 | 9-bit registered transceiver with parity generator/checker for FutureBus | three-state and open-collector | |||
74x989 | 1 | 64-bit RAM, inverting output | three-state | 16 | ||
74x990 | 1 | 8-bit D-type transparent read-back latch, non-inverting | three-state | 20 | ||
74x991 | 1 | 8-bit D-type transparent read-back latch, inverting | three-state | 20 | ||
74x992 | 1 | 9-bit D-type transparent read-back latch, non-inverting | three-state | 24 | ||
74x993 | 1 | 9-bit D-type transparent read-back latch, inverting | three-state | 24 | ||
74x994 | 1 | 10-bit D-type transparent read-back latch, non-inverting | three-state | 24 | ||
74x995 | 1 | 10-bit D-type transparent read-back latch, inverting | three-state | 24 | ||
74x996 | 1 | 8-bit D-type edge-triggered read-back latch | three-state | 24 | ||
Units | Description | Input | Output | Pins | Datasheet | |
74x1000 | 4 | quad 2-input NAND gate | driver | 14 | ||
74x1002 | 4 | quad 2-input NOR gate | driver | 14 | ||
74x1003 | 4 | quad 2-input NAND gate | open-collector driver | 14 | ||
74x1004 | 6 | hex inverting buffer | driver | 14 | ||
74x1005 | 6 | hex inverting buffer | open-collector driver | 14 | ||
74x1008 | 4 | quad 2-input AND gate | driver | 14 | ||
74ALS1010 | 3 | triple 3-input NAND gate | driver | 14 | ||
74AC1010 74ACT1010 | 1 | 16x16-bit multiplier/accumulator | three-state | 64 | ||
74x1011 | 3 | triple 3-input AND gate | driver | 14 | ||
74F1016 | 16 | 16-bit Schottky diode R-C bus termination array | ||||
74AC1016 74ACT1016 | 1 | 16x16-bit multiplier | three-state | 64 | ||
74x1017 | 1 | 16x16-bit parallel multiplier | three-state | 64 | ||
74x1018 | 18 | 18-bit Schottky diode R-C bus termination array | ||||
74x1020 | 2 | dual 4-input NAND gate | driver | 14 | ||
74x1032 | 4 | quad 2-input OR gate | driver | 14 | ||
74x1034 | 6 | hex non-inverting buffer | driver | 14 | ||
74x1035 | 6 | hex non-inverting buffer | open-collector driver | 14 | ||
74x1036 | 4 | quad 2-input NOR gate | driver | 14 | ||
74x1050 | 12 | 12-bit Schottky diode bus termination array, clamp to GND | 16 | |||
74x1051 | 12 | 12-bit Schottky diode bus termination array, clamp to GND/VCC | 16 | |||
74x1052 | 16 | 16-bit Schottky diode bus termination array, clamp to GND | 20 | |||
74x1053 | 16 | 16-bit Schottky diode bus termination array, clamp to GND/VCC | 20 | |||
74x1056 | 8 | 8-bit Schottky diode bus termination array, clamp to GND | ||||
74x1071 | 10 | 10-bit bus termination array with bus-hold function | ||||
74x1073 | 16 | 16-bit bus termination array with bus-hold function | ||||
74x1074 | 2 | dual D negative edge triggered flip-flop, asynchronous preset and clear | 14 | |||
74x1181 | 1 | 4-bit arithmetic logic unit | 24 | |||
74x1240 | 1 | octal buffer / line driver, inverting | three-state | 20 | ||
74x1241 | 1 | octal buffer / line driver, non-inverting | three-state | 20 | ||
74x1242 | 1 | quad bus transceiver, inverting | three-state | 14 | ||
74x1243 | 1 | quad bus transceiver, non-inverting | three-state | 14 | ||
74x1244 | 1 | octal buffer / driver, non-inverting | three-state | 20 | ||
74x1245 | 1 | octal bus transceiver | three-state | 20 | ||
74x1280 | 1 | 9-bit parity generator/checker with registered outputs | three-state | 20 | ||
74x1284 | 1 | parallel printer interface transceiver / buffer | 20 | |||
74x1403 | 1 | 8-bit bus receiver plus 4-bit bus driver | Schmitt-trigger | three-state | ||
74x1404 | 1 | oscillator driver | Schmitt-trigger | |||
74x1616 | 1 | 16x16-bit multimode multiplier | three-state | 64 | ||
74x1620 | 1 | octal bus transceiver, inverting | three-state | 20 | ||
74x1621 | 1 | octal bus transceiver, non-inverting | open-collector | 20 | ||
74x1622 | 1 | octal bus transceiver, inverting | open-collector | 20 | ||
74x1623 | 1 | octal bus transceiver, non-inverting | three-state | 20 | ||
74x1638 | 1 | octal bus transceiver, inverting | three-state and open-collector | 20 | ||
74x1639 | 1 | octal bus transceiver, non-inverting | three-state and open-collector | 20 | ||
74x1640 | 1 | octal bus transceiver, inverting | three-state | 20 | ||
74x1641 | 1 | octal bus transceiver, non-inverting | open-collector | 20 | ||
74x1642 | 1 | octal bus transceiver, inverting | open-collector | 20 | ||
74x1643 | 1 | octal bus transceiver, inverting and non-inverting | three-state | 20 | ||
74x1644 | 1 | octal bus transceiver, inverting and non-inverting | open-collector | 20 | ||
74x1645 | 1 | octal bus transceiver, non-inverting | three-state | 20 | ||
74x1650 | 2 | dual 9-bit Futurebus universal storage transceiver with split TTL I/O | three-state and open-collector | |||
74x1651 | 2 | 9-bit and 8-bit Futurebus universal storage transceivers with delayed buffered clock with split TTL I/O | three-state and open-collector | |||
74x1653 | 2 | 9-bit and 8-bit Futurebus universal storage transceivers with delayed buffered clock with split 3.3V TTL I/O | three-state and open-collector | |||
74x1665 | 2 | dual 8-bit GTL universal storage transceivers with live insertion | three-state and open-collector | |||
74x1760 | 1 | 10-bit 4-way latched address multiplexer | three-state | 64 | ||
74x1761 | 1 | dRAM and interrupt vector controller | 48 | |||
74x1762 | 1 | dRAM address controller | 40 | |||
74x1763 | 1 | single-port dRAM controller | 48 | |||
74x1764 | 1 | dual-port dRAM controller | 48 | |||
74x1765 | 1 | dual-port dRAM controller with address latch | 48 | |||
74x1801 | 1 | FM, MFM, and DM encoder / decoder, data rates up to 10 MHz | 24 | |||
74x1802 | 1 | SerDes with ECC and CRC, data rates up to 10 MHz | three-state | 48 | ||
74x1803 | 1 | quad clock driver | 14 | |||
74x1804 | 6 | hex 2-input NAND | driver | 20 | ||
74x1805 | 6 | hex 2-input NOR | driver | 20 | ||
74x1808 | 6 | hex 2-input AND | driver | 20 | ||
74x1811 | 1 | FM, MFM, and DM encoder / decoder, data rates up to 20 MHz | 24 | |||
74x1812 | 1 | SerDes with ECC and CRC, data rates up to 30 MHz | three-state | 48 | ||
74x1832 | 6 | hex 2-input OR | driver | 20 | ||
Units | Description | Input | Output | Pins | Datasheet | |
74x2000 | 1 | direction discriminator with microprocessor interface | three-state | 28 | ||
74x2003 | 1 | 8-bit level translator | ||||
74x2006 | 1 | 13-bit GTL to 3.3V TTL level translator | open-collector | |||
74x2007 | 1 | 12-bit GTL to 3.3V TTL level translator | open-collector | |||
74x2010 | 1 | 10-bit level translator | ||||
74x2014 | 1 | 4-bit GTL to TTL transceiver | three-state and open-collector | |||
74x2031 | 1 | 9-bit Futurebus address/data transceiver | three-state and open-collector | |||
74x2032 | 1 | 9-bit Futurebus competition transceiver | three-state and open-collector | |||
74x2033 | 1 | 8-bit Futurebus registered transceiver with split TTL I/O | three-state and open-collector | |||
74x2040 | 1 | 8-bit Futurebus transceiver with split TTL I/O | three-state and open-collector | |||
74x2041 | 1 | 7-bit Futurebus transceiver with split TTL I/O | three-state and open-collector | |||
74x2107 | 1 | 12-bit GTL to 3.3V TTL level translator | open-collector | |||
74x2125 | 4 | quad bus buffer | three-state, 25 Ω series resistor | |||
74x2151 | 1 | 8-line to 1-line multiplexer | 25 Ω series resistor | |||
74x2153 | 2 | dual 4-line to 1-line multiplexer | 25 Ω series resistor | |||
74x2157 | 4 | quad 2-line to 1-line multiplexer | 25 Ω series resistor | |||
74x2161 | 1 | synchronous presettable 4-bit binary counter, asynchronous clear | 25 Ω series resistor | 16 | ||
74x2163 | 1 | synchronous presettable 4-bit binary counter, synchronous clear | 25 Ω series resistor | 16 | ||
74x2191 | 1 | synchronous presettable 4-bit binary up/down counter, common clock | 25 Ω series resistor | 16 | ||
74x2193 | 1 | synchronous presettable 4-bit binary counter, separate up/down clocks | 25 Ω series resistor | 16 | ||
74x2226 | 2 | dual 64-bit FIFO memories | ||||
74x2227 | 2 | dual 64-bit FIFO memories | three-state | |||
74x2228 | 2 | dual 256-bit FIFO memories | ||||
74x2229 | 2 | dual 256-bit FIFO memories | three-state | |||
74x2232 | 1 | 512-bit FIFO memory | three-state | 24 | ||
74x2233 | 1 | 576-bit FIFO memory | three-state | 28 | ||
74x2235 | 1 | 18432-bit bidirectional FIFO memory | three-state | |||
74x2236 | 1 | 18432-bit bidirectional FIFO memory | three-state | |||
74x2238 | 1 | 576-bit bidirectional FIFO memory | three-state | 40 | ||
74x2240 | 2 | dual 4-bit bidirectional buffer / line driver, inverting | three-state, 25 Ω series resistor | 20 | ||
74x2241 | 2 | dual 4-bit bidirectional buffer / line driver, non-inverting | three-state, 25 Ω series resistor | 20 | ||
74x2242 | 1 | 4-bit bus transceiver, inverting | three-state, 25 Ω series resistor | 14 | ||
74x2243 | 1 | 4-bit bus transceiver, non-inverting | three-state, 25 Ω series resistor | |||
74x2244 | 2 | dual 4-bit buffer / line driver, non-inverting | three-state, 25 Ω series resistor | 20 | ||
74x2245 | 1 | octal bus transceiver | three-state, 25 Ω series resistor | 20 | ||
74x2253 | 2 | dual 4-line to 1-line multiplexer | three-state, 25 Ω series resistor | |||
74x2257 | 4 | quad 2-line to 1-line multiplexer | three-state, 25 Ω series resistor | |||
74x2273 | 8 | octal D-type flip-flop with common clock and reset | 25 Ω series resistor | |||
74x2299 | 1 | 8-bit universal shift register | three-state, 25 Ω series resistor | 20 | ||
74x2323 | 2 | dual line receiver | ||||
74x2373 | 1 | 8-bit transparent latch | three-state, 25 Ω series resistor | |||
74x2374 | 8 | octal D-type flip-flop with common clock | three-state, 25 Ω series resistor | |||
74x2377 | 1 | 8-bit register with clock enable | 25 Ω series resistor | 20 | ||
74x2400 | 2 | dual 4-bit buffer, inverting | Schmitt-trigger | three-state | 20 | |
74x2410 | 1 | 11-bit MOS memory driver, non-inverting | three-state, 25 Ω series resistor | 28 | ||
74x2411 | 1 | 11-bit MOS memory driver, inverting | three-state, 25 Ω series resistor | 28 | ||
74x2414 | 2 | dual 2-line to 4-line decoder with supply voltage monitor | 20 | |||
74x2420 | 1 | 16-bit NuBus address/data transceiver and register | three-state | |||
74x2423 | 1 | 16-bit latched multiplexer/demultiplexer NuBus transceiver, inverting | three-state | |||
74x2424 | 1 | 16-bit latched multiplexer/demultiplexer NuBus transceiver, non-inverting | three-state | |||
74x2425 | 1 | Macintosh Coprocessor Platform NuBus address/data registered transceiver | three-state | |||
74x2440 | 1 | NuBus interface controller | ||||
74x2441 | 1 | NuBus interface controller | ||||
74x2442 | 1 | NuBus block slave address generator | three-state | |||
74x2509 | 1 | 9-output clock driver with PLL | three-state | |||
74x2510 | 1 | 10-output clock driver with PLL | three-state | |||
74x2525 | 1 | 8-output clock driver | 14 | |||
74x2526 | 1 | 8-output clock driver with input multiplexer | 16 | |||
74x2533 | 1 | 8-bit bus interface latch, inverting | three-state, 25 Ω series resistor | 20 | ||
74x2534 | 1 | 8-bit bus interface register, inverting | three-state, 25 Ω series resistor | 20 | ||
74x2540 | 1 | 8-bit buffer / line driver, inverting | three-state, 25 Ω series resistor | 20 | ||
74x2541 | 1 | 8-bit buffer / line driver, non-inverting | three-state, 25 Ω series resistor | 20 | ||
74x2543 | 1 | 8-bit latched transceiver, non-inverting | three-state, 25 Ω series resistor | 24 | ||
74x2544 | 1 | 8-bit latched transceiver, inverting | three-state, 25 Ω series resistor | 24 | ||
74x2573 | 1 | 8-bit transparent latch | three-state, 25 Ω series resistor | 20 | ||
74x2574 | 8 | octal D-type flip-flop with common clock | three-state, 25 Ω series resistor | 20 | ||
74x2620 | 1 | octal bus transceiver / MOS driver, inverting | three-state, 25 Ω series resistor | 20 | ||
74x2623 | 1 | octal bus transceiver / MOS driver, non-inverting | three-state, 25 Ω series resistor | 20 | ||
74x2640 | 1 | octal bus transceiver / MOS driver, inverting | three-state, 25 Ω series resistor | 20 | ||
74x2643 | 1 | octal bus transceiver, mix of inverting and non-inverting outputs | three-state, 25 Ω series resistor | 20 | ||
74x2645 | 1 | octal bus transceiver / MOS driver, non-inverting | three-state, 25 Ω series resistor | 20 | ||
74x2646 | 1 | octal registered transceiver, non-inverting | three-state, 25 Ω series resistor | 24 | ||
74x2648 | 1 | octal registered transceiver, inverting | three-state, 25 Ω series resistor | 24 | ||
74x2651 | 1 | octal registered transceiver, inverting | three-state, 25 Ω series resistor | 24 | ||
74x2652 | 1 | octal registered transceiver, non-inverting | three-state, 25 Ω series resistor | 24 | ||
74S2708 | 1 | 8192-bit PROM | three-state | 24 | ||
74AC2708 | 1 | 576-bit FIFO memory | three-state | 28 | ||
74x2725 | 1 | 4608-bit FIFO memory | 28 | |||
74x2726 | 1 | 4608-bit bidirectional FIFO memory | 28 | |||
74x2821 | 1 | 10-bit D-type flip-flop | three-state, 25 Ω series resistor | 24 | ||
74x2823 | 1 | 9-bit D-type flip-flop with clear | three-state, 25 Ω series resistor | 24 | ||
74x2825 | 1 | 8-bit D-type flip-flop with clear and clock enable | three-state, 25 Ω series resistor | 24 | ||
74x2827 | 1 | 10-bit buffer, non-inverting | three-state, 25 Ω series resistor | 24 | ||
74x2828 | 1 | 10-bit buffer, inverting | three-state, 25 Ω series resistor | 24 | ||
74x2833 | 1 | 8-bit bus transceiver with parity error flip-flop | three-state, 25 Ω series resistor | 24 | ||
74x2841 | 1 | 10-bit transparent latch | three-state, 25 Ω series resistor | 24 | ||
74x2843 | 1 | 9-bit transparent latch with asynchronous reset | three-state, 25 Ω series resistor | 24 | ||
74x2845 | 1 | 8-bit transparent latch with asynchronous reset and multiple output enable | three-state, 25 Ω series resistor | 24 | ||
74x2853 | 1 | 8-bit bus transceiver with parity error latch | three-state, 25 Ω series resistor | 24 | ||
74x2861 | 1 | 10-bit non-inverting bus transceiver | three-state, 25 Ω series resistor | 24 | ||
74x2862 | 1 | 10-bit inverting bus transceiver | three-state, 25 Ω series resistor | 24 | ||
74x2863 | 1 | 9-bit non-inverting bus transceiver with dual output enable | three-state, 25 Ω series resistor | 24 | ||
74x2864 | 1 | 9-bit inverting bus transceiver with dual output enable | three-state, 25 Ω series resistor | 24 | ||
74x2952 | 1 | octal bus transceiver and register, non-inverting | three-state | 24 | ||
74x2953 | 1 | octal bus transceiver and register, inverting | three-state | 24 | ||
74x2960 | 1 | error detection and correction, equivalent to Am2960 | three-state | 48 | ||
74x2961 | 1 | 4-bit EDAC bus buffer, inverting, equivalent to Am2961 | three-state | 24 | ||
74x2962 | 1 | 4-bit EDAC bus buffer, non-inverting, equivalent to Am2962 | three-state | 24 | ||
74x2967 | 1 | controller/driver for 16k/64k/256k dRAM | 48 | |||
74x2968 | 1 | controller/driver for 16k/64k/256k dRAM | 48 | |||
74x2969 | 1 | memory timing controller for use with EDAC | 48 | |||
74x2970 | 1 | memory timing controller for use without EDAC | 24 | |||
74x3004 | 1 | selectable GTL voltage reference | ||||
74x3037 | 4 | quad 2-input NAND | driver 30 Ω | 16 | ||
74x3038 | 4 | quad 2-input NAND | open-collector driver 30 Ω | 16 | ||
74x3040 | 2 | dual 4-input NAND | driver 30 Ω | 16 | ||
74x3125 | 4 | quad FET bus switch, output enable active low | ||||
74x3126 | 4 | quad FET bus switch, output enable active high | ||||
74FCT3244 | 2 | dual 4-bit buffer / line driver | three-state | 20 | ||
74CBT3244 74FST3244 | 2 | dual 4-bit FET bus switch | 20 | |||
74FCT3245 | 1 | octal bidirectional transceiver | three-state | 20 | ||
74CBT3245 74FST3245 | 1 | octal FET bus switch | 20 | |||
74LVX3245 | 1 | octal bidirectional voltage-translating transceiver | three-state | |||
74x3251 | 1 | 8-line to 1-line FET multiplexer / demultiplexer | ||||
74x3253 | 2 | dual 4-line to 1-line FET multiplexer / demultiplexer | ||||
74x3257 | 4 | quad 2-line to 1-line FET multiplexer / demultiplexer | ||||
74x3283 | 1 | 32-bit latchable transceiver with parity checker / generator | three-state | |||
74x3284 | 1 | 18-bit synchronous datapath multiplexer | three-state | |||
74x3305 | 2 | dual FET bus switch with extended voltage range | ||||
74x3306 | 2 | dual FET bus switch | ||||
74x3345 | 1 | octal FET bus switch, dual output enable | ||||
74x3383 | 1 | 5-bit 4-port FET bus exchange switch | 24 | |||
74x3384 | 2 | dual 5-bit FET bus switch | 24 | |||
74x3386 | 1 | 5-bit 4-port FET bus exchange switch with extended voltage range | ||||
74x3390 | 1 | octal 2-line to 1-line FET multiplexer / bus switch | ||||
74x3573 | 1 | octal transparent latch | three-state | 20 | ||
74x3574 | 1 | octal D-type flip flop | three-state | 20 | ||
74x3584 | 2 | dual 5-bit FET bus switch | 24 | |||
74x3611 | 1 | 2304-bit FIFO memory | three-state | |||
74x3612 | 1 | 4608-bit bidirectional FIFO memory | three-state | |||
74x3613 | 1 | 2304-bit FIFO memory | three-state | |||
74x3614 | 1 | 4608-bit bidirectional FIFO memory | three-state | |||
74x3622 | 1 | 18432-bit bidirectional FIFO memory | three-state | |||
74x3631 | 1 | 18432-bit FIFO memory | three-state | |||
74x3632 | 1 | 36864-bit bidirectional FIFO memory | three-state | |||
74x3638 | 1 | 32768-bit bidirectional FIFO memory | three-state | |||
74x3641 | 1 | 36864-bit FIFO memory | three-state | |||
74x3642 | 1 | 73728-bit bidirectional FIFO memory | three-state | |||
74x3651 | 1 | 73728-bit FIFO memory | three-state | |||
74x3708 | 1 | 8192-bit PROM | open-collector | 24 | ||
74x3807 | 1 | 1-to-10 clock driver | driver | 20 | ||
74x3827 | 1 | 10-bit buffer | three-state | 24 | ||
74x3861 | 1 | 10-bit FET bus switch | ||||
74x3862 | 1 | 10-bit FET bus switch with dual output enable | ||||
74x3893 | 1 | quad Futurebus backplane transceiver | three-state and open-collector | |||
74x3907 | 1 | Pentium clock synthesizer | three-state | |||
74x3932 | 1 | PLL-based clock driver | three-state | |||
Units | Description | Input | Output | Pins | Datasheet | |
74x4002 | 2 | dual 4-input NOR gate | 14 | |||
74x4015 | 2 | dual 4-bit shift registers | 16 | |||
74x4016 | 4 | quad bilateral switch | analog | 14 | ||
74x4017 | 1 | 5-stage ÷10 Johnson counter | 16 | |||
74x4020 | 1 | 14-stage binary counter | 16 | |||
74x4022 | 1 | 4-stage ÷8 Johnson counter | 14 | |||
74x4024 | 1 | 7-stage ripple carry binary counter | 14 | |||
74x4028 | 1 | BCD to decimal decoder | 16 | |||
74x4040 | 1 | 12-stage binary ripple counter | 16 | |||
74x4046 | 1 | phase-locked loop and voltage-controlled oscillator | 16 | |||
74x4049 | 6 | hex inverting buffer | 16 | |||
74x4050 | 6 | hex buffer/converter | 16 | |||
74x4051 | 1 | high-speed 8-channel analog multiplexer/demultiplexer | analog | 16 | ||
74x4052 | 2 | dual 4-channel analog multiplexer/demultiplexers | analog | 16 | ||
74x4053 | 3 | triple 2-channel analog multiplexer/demultiplexers | analog | 16 | ||
74x4059 | 1 | programmable divide-by-N counter | 24 | |||
74x4060 | 1 | 14-stage binary ripple counter with oscillator | 16 | |||
74x4061 | 1 | 14-stage asynchronous binary counter with oscillator | 16 | |||
74x4066 | 4 | quad single-pole single-throw analog switch | 14 | |||
74x4067 | 1 | 16-channel analog multiplexer/demultiplexer | analog | 24 | ||
74x4072 | 2 | dual 4-input OR gate | 14 | |||
74x4075 | 3 | triple 3-input OR gate | 14 | |||
74x4078 | 1 | 8-input OR/NOR gate | 14 | |||
74x4094 | 1 | 8-bit three-state shift register/latch | three-state | 16 | ||
74x4245 | 1 | 8-bit 3V/5V translating transceiver | three-state | |||
74x4301 | 1 | 8-bit latch, inverting | three-state | 20 | ||
74x4302 | 1 | 8-bit latch, non-inverting | three-state | 20 | ||
74x4303 | 1 | 8-bit D-type flip-flop, inverting outputs | three-state | 20 | ||
74x4304 | 1 | 8-bit D-type flip-flop, non-inverting outputs | three-state | 20 | ||
74x4305 | 2 | dual 4-bit buffer, inverting | three-state | 20 | ||
74x4306 | 2 | dual 4-bit buffer, non-inverting | three-state | 20 | ||
74x4316 | 4 | quad analog switch | analog | 14 | ||
74x4351 | 1 | 8-channel analog multiplexer/demultiplexer with latch | analog | 20 | ||
74x4352 | 2 | dual 4-channel analog multiplexer/demultiplexer with latch | analog | 20 | ||
74x4353 | 3 | triple 2-channel analog multiplexer/demultiplexer with latch | analog | 20 | ||
74x4510 | 1 | BCD decade up/down counter | 16 | |||
74x4511 | 1 | BCD to 7-segment decoder | 16 | |||
74x4514 | 1 | 4-to-16 line decoder/demultiplexer, input latches | 24 | |||
74x4515 | 1 | 4-to-16 line decoder/demultiplexer with input latches; inverting | 24 | |||
74x4516 | 1 | 4-bit binary up/down counter | 16 | |||
74x4518 | 2 | dual 4-bit synchronous decade counter | 16 | |||
74x4520 | 2 | dual 4-bit synchronous binary counter | 16 | |||
74x4538 | 2 | dual retriggerable precision monostable multivibrator | 16 | |||
74x4543 | 1 | BCD to 7-segment latch/decoder/driver for LCDs | 16 | |||
74x4560 | 1 | 4-bit BCD adder | 16 | |||
74x4724 | 1 | 8-bit addressable latch | 16 | |||
74x4764 | 1 | programmable dRAM controller | ||||
74x4799 | 1 | Timer for NiCd and NiMH chargers | Schmitt-trigger | open-collector and three-state | 16 | |
74x4851 | 1 | 8-channel analog multiplexer/demultiplexer | analog | 16 | ||
74x4852 | 2 | dual 4-channel analog multiplexer/demultiplexer | analog | 16 | ||
74x5074 | 2 | dual positive edge-triggered D-type flip-flop | 14 | |||
74x5245 | 1 | octal bidirectional transceiver | Schmitt-trigger | three-state | 20 | |
74x5300 | 1 | LED driver | driver 120 mA | |||
74x5400 | 1 | 11-bit line/memory driver, non-inverting | three-state, 25 Ω series resistor | 28 | ||
74x5401 | 1 | 11-bit line/memory driver, inverting | three-state, 25 Ω series resistor | 28 | ||
74x5402 | 1 | 12-bit line/memory driver, non-inverting | three-state, 25 Ω series resistor | 28 | ||
74x5403 | 1 | 12-bit line/memory driver, inverting | three-state, 25 Ω series resistor | 28 | ||
74x5555 | 1 | programmable delay timer with oscillator | 16 | |||
74x5620 | 1 | octal bidirectional transceiver | Schmitt-trigger | three-state | 20 | |
74x6000 | 1 | logic-to-logic optocoupler, non-inverting | 6 | |||
74x6001 | 1 | logic-to-logic optocoupler, inverting | 6 | |||
74x6010 | 1 | logic-to-logic optocoupler, non-inverting | open-collector 15 V | 6 | ||
74x6011 | 1 | logic-to-logic optocoupler, inverting | open-collector 15 V | 6 | ||
74x6301 | 1 | dynamic memory refresh controller, transparent and burst modes, for 16K, 64K, 256K, and 1M dRAM | 52 | |||
74x6302 | 1 | dynamic memory refresh controller, transparent and burst modes, for 16K, 64K, 256K, and 1M dRAM | 52 | |||
74x6323 | 1 | programmable ripple counter with oscillator | three-state | |||
74x6800 | 1 | 10-bit FET bus switch with precharge | 24 | |||
74x6845 | 1 | 8-bit FET bus switch with precharge and extended voltage range | ||||
74x7001 | 4 | quad 2-input AND gate | Schmitt-trigger | 14 | ||
74x7002 | 4 | quad 2-input NOR gate | Schmitt-trigger | 14 | ||
74x7006 | 6 | two inverters, one 3-input NAND, one 4-input NAND, one 3-input NOR, one 4-input NOR | 24 | |||
74x7007 | 6 | hex buffer | 14 | |||
74x7008 | 6 | two inverters, three 2-input NAND, three 2-input NOR | 24 | |||
74x7014 | 6 | hex non-inverting buffer | Schmitt-trigger | 14 | ||
74x7022 | 1 | 4-stage ÷8 Johnson counter with power-up clear | 14 | |||
74x7030 | 1 | 576-bit FIFO memory | three-state | 28 | ||
74x7032 | 4 | quad 2-input OR gates | Schmitt-trigger | 14 | ||
74x7038 | 1 | 9-bit bus transceiver with latch | three-state | 24 | ||
74x7046 | 1 | phase-locked loop with voltage-controlled oscillator and lock detector | 16 | |||
74x7074 | 6 | two inverters, one 2-input NAND, one 2-input NOR, two D-type flip-flops | 24 | |||
74x7075 | 6 | two inverters, two 2-input NAND, two D-type flip-flops | 24 | |||
74x7076 | 6 | two inverters, two 2-input NOR, two D-type flip-flops | 24 | |||
74x7080 | 1 | 16-bit parity generator / checker | 20 | |||
74x7132 | 4 | quad adjustable comparator with output latches | Schmitt-trigger | three-state | 14 | |
74x7200 | 1 | 2304-bit FIFO memory | 28 | |||
74x7201 | 1 | 4608-bit FIFO memory | 28 | |||
74x7202 | 1 | 9216-bit FIFO memory | 28 | |||
74x7203 | 1 | 18432-bit FIFO memory | 28 | |||
74ACT7204 | 1 | 36864-bit FIFO memory | 28 | |||
74HCU7204 | 2 | dual unbuffered inverters | ||||
74x7205 | 1 | 73728-bit FIFO memory | 28 | |||
74x7206 | 1 | 147456-bit FIFO memory | 28 | |||
74x7240 | 1 | octal bus buffer, inverting | Schmitt-trigger | three-state | 20 | |
74x7241 | 1 | octal bus buffer, non-inverting | Schmitt-trigger | three-state | 20 | |
74x7244 | 1 | octal bus buffer, non-inverting | Schmitt-trigger | three-state | 20 | |
74x7245 | 1 | octal bus transceiver, non-inverting | Schmitt-trigger | three-state | 20 | |
74x7266 | 4 | quad 2-input XNOR gate | 14 | |||
74x7273 | 8 | octal positive edge-triggered D-type flip-flop with reset | open-collector | 20 | ||
74x7292 | 1 | programmable divider/timer | 16 | |||
74x7294 | 1 | programmable divider/timer | 16 | |||
74x7340 | 1 | 8-bit bus driver with bidirectional registers | three-state | 24 | ||
74x7403 | 1 | 256-bit FIFO memory | three-state | 16 | ||
74x7404 | 1 | 320-bit FIFO memory | three-state | 18 | ||
74x7540 | 8 | octal buffer/line driver, inverting | Schmitt-trigger | three-state | 20 | |
74x7541 | 8 | octal buffer/line driver, non-inverting | Schmitt-trigger | three-state | 20 | |
74x7597 | 1 | 8-bit shift register with input latches | 16 | |||
74x7640 | 1 | octal bus transceiver, inverting | Schmitt-trigger | three-state | 20 | |
74x7643 | 1 | octal bus transceiver, non-inverting/inverting | Schmitt-trigger | three-state | 20 | |
74x7645 | 1 | octal bus transceiver, non-inverting | Schmitt-trigger | three-state | 20 | |
74x7731 | 4 | quad 64-bit static shift register | 16 | |||
74x7793 | 1 | 8-bit noninverting transparent latch with readback | three-state | 20 | ||
74x7801 | 1 | 18432-bit FIFO memory, clocked | three-state | |||
74x7802 | 1 | 18432-bit FIFO memory | three-state | |||
74x7803 | 1 | 9216-bit FIFO memory, clocked | three-state | |||
74x7804 | 1 | 9216-bit FIFO memory | three-state | |||
74x7805 | 1 | 4608-bit FIFO memory, clocked | three-state | |||
74x7806 | 1 | 4608-bit FIFO memory | three-state | |||
74x7807 | 1 | 18432-bit FIFO memory, clocked | three-state | |||
74x7808 | 1 | 18432-bit FIFO memory | three-state | |||
74x7811 | 1 | 18432-bit FIFO memory, clocked | three-state | |||
74x7813 | 1 | 1152-bit FIFO memory, clocked | three-state | |||
74x7814 | 1 | 1152-bit FIFO memory | three-state | |||
74x7815 | 1 | 4608-bit bidirectional FIFO memory | three-state | |||
74x7816 | 1 | 4608-bit bidirectional FIFO memory | three-state | |||
74x7817 | 1 | 2304-bit FIFO memory | three-state | |||
74x7818 | 1 | 2304-bit FIFO memory | three-state | |||
74x7819 | 1 | 18432-bit bidirectional FIFO memory, clocked | three-state | |||
74x7820 | 1 | 18432-bit bidirectional FIFO memory | three-state | |||
74x7821 | 1 | 32768-bit bidirectional FIFO memory | three-state | |||
74x7822 | 1 | 32768-bit bidirectional FIFO memory, clocked | three-state | |||
74x7823 | 1 | 36864-bit FIFO memory, clocked | three-state | |||
74x7881 | 1 | 18432-bit FIFO memory, clocked | three-state | |||
74x7882 | 1 | 36864-bit FIFO memory, clocked | three-state | |||
74x7884 | 1 | 73728-bit FIFO memory, clocked | three-state | |||
74x8003 | 2 | dual 2-input NAND gate | 8 | |||
74x8151 | 1 | 10-bit inverting/non-inverting buffer | Schmitt-trigger | three-state | 24 | |
74x8153 | 1 | 8-bit serial-to-parallel interface | three-state or open-collector | 20 | ||
74x8154 | 2 | dual 16-bit counters with output registers | three-state | 20 | ||
74x8240 | 1 | octal inverting buffer with JTAG port | three-state | 24 | ||
74x8244 | 1 | octal non-inverting buffer with JTAG port | three-state | 24 | ||
74x8245 | 1 | octal bus transceiver with JTAG port | three-state | 24 | ||
74x8373 | 1 | octal D-type latch with JTAG port | three-state | 24 | ||
74x8374 | 1 | octal D-type edge-triggered flip-flop with JTAG port | three-state | 24 | ||
74x8400 | 1 | expandable error checker / corrector | three-state | 48 | ||
74x8541 | 1 | 8-bit buffer, selectable inverting/non-inverting | Schmitt-trigger | three-state | 20 | |
74x8543 | 1 | octal registered bus transceiver with JTAG port | three-state | 28 | ||
74x8646 | 1 | octal bus transceiver and register with JTAG port | three-state | 28 | ||
74x8652 | 1 | octal bus transceiver and register with JTAG port | three-state | 28 | ||
74x8814 | 1 | 16-bit microprogram sequencer, cascadable | three-state | |||
74x8832 | 1 | 32-bit registered ALU | three-state | |||
74x8834 | 1 | 40-bit register file | three-state | |||
74x8835 | 1 | 16-bit microprogram sequencer, cascadable | three-state | |||
74x8836 | 1 | 32x32-bit multiplier/accumulator | three-state | |||
74x8837 | 1 | 64-bit floating point unit | three-state | |||
74x8838 | 1 | 64-bit barrel shifter | three-state | |||
74x8839 | 1 | 32-bit shuffle/exchange network | three-state | |||
74x8840 | 1 | digital crossbar switch | three-state | |||
74x8841 | 1 | digital crossbar switch | three-state | |||
74x8847 | 1 | 64-bit floating point and integer unit | three-state | |||
74x8952 | 1 | octal registered bus transceiver with JTAG port | three-state | 28 | ||
74x8980 | 1 | JTAG test access port master with 8-bit host interface | three-state | 24 | ||
74x8986 | 1 | linkable, multidrop-addressable JTAG transceiver | three-state | |||
74x8990 | 1 | JTAG test access port master with 16-bit host interface | three-state | |||
74x8994 | 1 | JTAG scan-controlled logic/signature analyzer | ||||
74x8996 | 1 | multidrop-addressable JTAG transceiver | 24 | |||
74x8997 | 1 | scan-controlled JTAG concatenator | three-state | 28 | ||
74x8999 | 1 | scan-controlled JTAG multiplexer | three-state | 28 | ||
74x9000 | 1 | programmable timer with oscillator | 20 | |||
74x9014 | 9 | nine-wide buffer/line driver, inverting | Schmitt-trigger | 20 | ||
74x9015 | 9 | nine-wide buffer/line driver, non-inverting | Schmitt-trigger | 20 | ||
74x9034 | 9 | nine-wide buffer, inverting | 20 | |||
74x9035 | 9 | nine-wide buffer, noninverting | 20 | |||
74x9046 | 1 | PLL with band gap controlled VCO | 16 | |||
74x9114 | 9 | nine-wide inverter | Schmitt-trigger | open-collector | 20 | |
74x9115 | 9 | nine-wide buffer | Schmitt-trigger | open-collector | 20 | |
74x9134 | 9 | nine-wide buffer, inverting | open-collector | 20 | ||
74x9135 | 9 | nine-wide buffer, noninverting | open-collector | 20 | ||
74x9164 | 1 | 8-bit shift register | Schmitt-trigger | three-state | ||
74x9240 | 1 | 9-bit buffer / line driver, inverting | three-state | 24 | ||
74x9244 | 1 | 9-bit buffer / line driver, non-inverting | three-state | 24 | ||
74x9245 | 1 | 9-bit bidirectional transceiver, non-inverting | three-state | 24 | ||
74x9323 | 1 | programmable ripple counter with oscillator | three-state | |||
74x9595 | 1 | 8-bit shift register with latch | Schmitt-trigger | |||
74x40102 | 1 | presettable synchronous 2-decade BCD down counter | 16 | |||
74x40103 | 1 | presettable 8-bit synchronous down counter | 16 | |||
74x40104 | 4 | 4-bit bidirectional universal shift register | three-state | 16 | ||
74x40105 | 1 | 64-bit FIFO memory | three-state | 16 | ||
Part number | Units | Description | Input | Output | Pins | Datasheet |
Smaller footprints
As board designs have migrated away from large amounts of logic chips, so has the need for many of the same gate in one package. Since about 1996, there has been an ongoing trend towards one / two / three logic gates per chip. Now logic can be placed where it is physically needed on a board, instead of running long signal traces to a full-size logic chip that has many of the same gate.All chips in the following sections are available 4 to 12 pin surface mount packages. The right digits, after the 1G/2G/3G, typically has the same functional features as older legacy chips, except for the multifunctional chips and 4-digit chip numbers which are unique to these newer families. The "x" in the part number is a place holder for the logic family name. For example, 74x1G14 in "LVC" logic family would be "74LVC1G14". The previously stated prefixes of "SN-" and "MC-" are used to denote manufacturers, Texas Instruments and ON Semiconductor respectively.
Some of the manufacturers that make these smaller IC chips are: Diodes Incorporated, Nexperia, ON Semiconductor, Texas Instruments, Toshiba.
One gate chips
All chips in this section have one gate, noted by the "1G" in the part numbers. The most popular logic families are LVC and AUP, however there have been other releases such as AUC and AXP families with shorter propagation delays or expansions of the existing families such as the AHC and HC.Part number | Description | Input | Output | Datasheet |
74x1G00 | single 2-input NAND gate | |||
74x1G02 | single 2-input NOR gate | |||
74x1G03 | Single 2-input NAND gate with open drain output | open-drain | ||
74x1G04 | single inverter gate | |||
74x1G06 | single inverter gate | schmitt-trigger | open-drain | |
74x1G07 | single buffer gate | schmitt-trigger | open-drain | |
74x1G08 | single 2-input AND gate | |||
74x1G09 | single 2-input AND gate | open-drain | ||
74x1G14 | single inverter gate | schmitt-trigger | ||
74x1G17 | single buffer gate | schmitt-trigger | ||
74x1G27 | single 3-input NOR gate | |||
74x1G32 | single 2-input OR gate | |||
74x1G34 | single buffer gate | |||
74x1G57 | single configurable 7-function gate | schmitt-trigger | ||
74x1G58 | single configurable 7-function gate | schmitt-trigger | ||
74x1G79 | single D-type flip-flop, positive-edge trigger | |||
74x1G80 | single D-type flip-flop, positive-edge trigger, inverted output | |||
74x1G86 | single 2-input XOR gate | |||
74x1G97 | single configurable 7-function gate | schmitt-trigger | ||
74x1G98 | single configurable 7-function gate | schmitt-trigger | ||
74x1G99 | single configurable 15-function gate, active-low enable | schmitt-trigger | three-state | |
74x1G123 | single retriggerable monostable multivibrator, clear | |||
74x1G125 | single buffer gate, active-low enable | three-state | ||
74x1G126 | single buffer gate, active-high enable | three-state | ||
74x1G157 | single 2-input multiplexer | schmitt-trigger | ||
74x1G158 | single 2-input multiplexer, inverted output | schmitt-trigger | ||
74x1G175 | single D-type flip-flop, positive-edge trigger, asynchronous clear | |||
74x1G373 | single transparent latch, active-low enable | three-state | ||
74x1G374 | single D-type flip-flop, active-low enable | three-state | ||
74x1G386 | single 3-input XOR Gate | |||
74x1G0832 | single 3-input AND-OR combo gate | schmitt-trigger | ||
74x1G3157 | single-pole double-throw analog switch | analog | ||
74x1G3208 | single 3-input OR-AND combo gate | schmitt-trigger |
Two gate chips
All chips in this section have two gates, noted by the "2G" in the part numbers. The "2G" chips mainly consist of AUG and LVC logic families, more recently AHC, AHCT, HC, HCT families have been expanding, plus some support for AXP family.Part number | Description | Input | Output | Datasheet |
74x2G00 | dual 2-input NAND gate | |||
74x2G02 | dual 2-input NOR gate | |||
74x2G04 | dual inverter gate | |||
74x2G06 | dual inverter gate | schmitt-trigger | open-drain | |
74x2G07 | dual buffer gate | schmitt-trigger | open-drain | |
74x2G08 | dual 2-input AND gate | |||
74x2G14 | dual inverter gate | schmitt-trigger | ||
74x2G17 | dual buffer gate | schmitt-trigger | ||
74x2G32 | dual 2-input OR gate | |||
74x2G34 | dual buffer gate | |||
74x2G57 | dual configurable 7-function gate | schmitt-trigger | ||
74x2G58 | dual configurable 7-function gate | schmitt-trigger | ||
74x2G79 | dual D-type flip-flop, positive-edge trigger | |||
74x2G80 | dual D-type flip-flop, positive-edge trigger, invert output | |||
74x2G97 | dual configurable 7-function gate | schmitt-trigger | ||
74x2G98 | dual configurable 7-function gate | schmitt-trigger | ||
74x2G125 | dual buffer, active-low enable | three-state | ||
74x2G126 | dual buffer, active-high enable | three-state | ||
74x2G240 | dual inverter, active-low enable, | three-state | ||
74x2G241 | dual buffer, active-low and active-high enables | three-state | ||
74x2G0604 | dual combo gates - one inverter, one inverter with O.D. | open-drain | ||
74x2G3404 | dual combo gates - one buffer, one inverter | |||
74x2G3407 | dual combo gates - one buffer, one buffer with O.D. | open-drain |
Three gate chips
All chips in this section have three gates, noted by the "3G" in the part numbers. The "3G" chips mainly consist of AUG and LVC logic families, more recently AHC, AHCT, HC, HCT families have been expanding.Part number | Description | Input | Output | Datasheet |
74x3G04 | triple inverter gate | |||
74x3G06 | triple inverter gate | schmitt-trigger | open-drain | |
74x3G07 | triple buffer gate | schmitt-trigger | open-drain | |
74x3G14 | triple inverter gate | schmitt-trigger | ||
74x3G16 | triple buffer gate | |||
74x3G17 | triple buffer gate | schmitt-trigger | ||
74x3G34 | triple buffer gate | |||
74x3G0434 | triple combo gates - two inverter, one buffer | |||
74x3G3404 | triple combo gates - two buffer, one inverter |